inference/research
verifiedhigh · 0.90updated 2026-10-03

AMD Instinct MI300A

amd CDNA3 (gfx942) 2023

Fields

id
accelerators/amd-instinct-mi300a
Vendor
amd
Architecture
CDNA3 (gfx942)
Release year
2023
Process (nm)
5
Form factors
socs
VRAM (GB)
128
Memory type
hbm3
Memory bus (bit)
8,192
Memory bandwidth (GB/s)
5,300
Bandwidth basis
Same derivation as MI300X: 8192-bit x 5.2 Gbps / 8 = 5,324.8 GB/s, published as '5.3 TB/s'. Six XCDs instead of eight, but the aggregate memory interface is still 8192-bit.
Peak FLOPS
precisionfp32tflops122.6denseyesvendor_claimyessource_idamd-mi300a-product-pagebasisvendor-spec-sheetbasis_detailTranscribed from the vendor's own fp32 for AMD Instinct MI300A (source of record: 'AMD Instinct MI300A product page', kind: spec-sheet). Recorded dense:true as printed.precisiontf32tflops490.3denseyesvendor_claimyessource_idamd-mi300a-product-pagebasisvendor-spec-sheetbasis_detailTranscribed from the vendor's own tf32 for AMD Instinct MI300A (source of record: 'AMD Instinct MI300A product page', kind: spec-sheet). Recorded dense:true as printed.precisiontf32tflops980.6densenovendor_claimyessource_idamd-mi300a-product-pagebasisvendor-spec-sheetbasis_detailTranscribed from the vendor's own tf32 for AMD Instinct MI300A (source of record: 'AMD Instinct MI300A product page', kind: spec-sheet). Recorded dense:false - the vendor prints this as a structured-sparsity figure; the dense companion row on this record is the halved value. See this record's notes for the sparsity-footnote rule.precisionfp16tflops980.6denseyesvendor_claimyessource_idamd-mi300a-product-pagebasisvendor-spec-sheetbasis_detailTranscribed from the vendor's own fp16 for AMD Instinct MI300A (source of record: 'AMD Instinct MI300A product page', kind: spec-sheet). Recorded dense:true as printed.precisionfp16tflops1,960densenovendor_claimyessource_idamd-mi300a-product-pagebasisvendor-spec-sheetbasis_detailTranscribed from the vendor's own fp16 for AMD Instinct MI300A (source of record: 'AMD Instinct MI300A product page', kind: spec-sheet). Recorded dense:false - the vendor prints this as a structured-sparsity figure; the dense companion row on this record is the halved value. See this record's notes for the sparsity-footnote rule.precisionbf16tflops980.6denseyesvendor_claimyessource_idamd-mi300a-product-pagebasisvendor-spec-sheetbasis_detailTranscribed from the vendor's own bf16 for AMD Instinct MI300A (source of record: 'AMD Instinct MI300A product page', kind: spec-sheet). Recorded dense:true as printed.precisionbf16tflops1,960densenovendor_claimyessource_idamd-mi300a-product-pagebasisvendor-spec-sheetbasis_detailTranscribed from the vendor's own bf16 for AMD Instinct MI300A (source of record: 'AMD Instinct MI300A product page', kind: spec-sheet). Recorded dense:false - the vendor prints this as a structured-sparsity figure; the dense companion row on this record is the halved value. See this record's notes for the sparsity-footnote rule.precisionfp8tflops1,960denseyesvendor_claimyessource_idamd-mi300a-product-pagebasisvendor-spec-sheetbasis_detailTranscribed from the vendor's own fp8 for AMD Instinct MI300A (source of record: 'AMD Instinct MI300A product page', kind: spec-sheet). Recorded dense:true as printed.precisionfp8tflops3,920densenovendor_claimyessource_idamd-mi300a-product-pagebasisvendor-spec-sheetbasis_detailTranscribed from the vendor's own fp8 for AMD Instinct MI300A (source of record: 'AMD Instinct MI300A product page', kind: spec-sheet). Recorded dense:false - the vendor prints this as a structured-sparsity figure; the dense companion row on this record is the halved value. See this record's notes for the sparsity-footnote rule.precisionint8tflops1,960denseyesvendor_claimyessource_idamd-mi300a-product-pagebasisvendor-spec-sheetbasis_detailTranscribed from the vendor's own int8 for AMD Instinct MI300A (source of record: 'AMD Instinct MI300A product page', kind: spec-sheet). Recorded dense:true as printed.precisionint8tflops3,920densenovendor_claimyessource_idamd-mi300a-product-pagebasisvendor-spec-sheetbasis_detailTranscribed from the vendor's own int8 for AMD Instinct MI300A (source of record: 'AMD Instinct MI300A product page', kind: spec-sheet). Recorded dense:false - the vendor prints this as a structured-sparsity figure; the dense companion row on this record is the halved value. See this record's notes for the sparsity-footnote rule.
TDP (W)
550
Unified memory
yes
Consumer part
no
notes
AUDIT 2026-10-03 (AMD convention check, no values changed): AMD's 'Peak X Performance' = DENSE / 'with Structured Sparsity' = SPARSE at 2x rule (source acc2-amd-ml300-convention) is confirmed on the MI300A page itself: FP8 '1.96 PFLOPs' dense / '3.92 PFLOPs' sparse, FP16 980.6/1.96 PFLOPs, TF32 490.3/980.6, INT8 1.96 POPs/3.92 POPs, BF16 980.6/1.96 PFLOPs. Every dense flag on this record is correct. THE UNUSUAL THING ABOUT THIS PART, and the reason it is not interchangeable with the MI300X despite the same 8192-bit bus and the same published 5.3 TB/s: MI300A is an APU, and AMD prints BOTH 'Thermal Design Power (TDP) 550W' and '760W Peak' for it, and prints 'Thermal Design Power (TDP) 750W Peak' for the MI300X. So tdp_w 550 here is the sustained TDP and the 760 W peak is a different, higher number that a reader budgeting power must not confuse with it. Both parts have the same 128 GB vs 192 GB memory split this repo records, and the MI300A's 550 W is its distinguishing figure for an inference server: lower peak power than the MI300X at 0.75 the memory, which is the whole argument for it in a power-capped box. An APU, not a discrete GPU: 24 Zen 4 CPU cores plus 6 GPU XCDs (228 CUs) and 3 CCDs on one SH5 socket package. unified_memory is true in the practical sense - the 128 GB HBM3 is coherent with the CPU cores on the same package, which is the entire point of the part for CPU+GPU shared-memory inference. Compute is exactly 3/4 of MI300X (228 vs 304 CUs; 980.6 vs 1307.4 TFLOPS FP16 dense), consistent with 6 XCDs vs 8. Memory capacity is 2/3 of MI300X. Transistor count 146B vs 153B. TDP 550W (760W peak), about 200W below the MI300X OAM. SH5 socket rather than an OAM module; passive + active cooling. Form-factor caveat for inference sizing: a socketed part with 128GB of coherent CPU+GPU memory can serve mid-size models without the cost of an 8-GPU platform, but it is not an OAM and cannot be assembled into a UBB Infinity Fabric mesh in the same way. 8 Infinity Fabric links at 128 GB/s are listed but the platform story differs. ROCm LLVM target gfx942.

Notes

AUDIT 2026-10-03 (AMD convention check, no values changed): AMD's 'Peak X Performance' = DENSE / 'with Structured Sparsity' = SPARSE at 2x rule (source acc2-amd-ml300-convention) is confirmed on the MI300A page itself: FP8 '1.96 PFLOPs' dense / '3.92 PFLOPs' sparse, FP16 980.6/1.96 PFLOPs, TF32 490.3/980.6, INT8 1.96 POPs/3.92 POPs, BF16 980.6/1.96 PFLOPs. Every dense flag on this record is correct. THE UNUSUAL THING ABOUT THIS PART, and the reason it is not interchangeable with the MI300X despite the same 8192-bit bus and the same published 5.3 TB/s: MI300A is an APU, and AMD prints BOTH 'Thermal Design Power (TDP) 550W' and '760W Peak' for it, and prints 'Thermal Design Power (TDP) 750W Peak' for the MI300X. So tdp_w 550 here is the sustained TDP and the 760 W peak is a different, higher number that a reader budgeting power must not confuse with it. Both parts have the same 128 GB vs 192 GB memory split this repo records, and the MI300A's 550 W is its distinguishing figure for an inference server: lower peak power than the MI300X at 0.75 the memory, which is the whole argument for it in a power-capped box. An APU, not a discrete GPU: 24 Zen 4 CPU cores plus 6 GPU XCDs (228 CUs) and 3 CCDs on one SH5 socket package. unified_memory is true in the practical sense - the 128 GB HBM3 is coherent with the CPU cores on the same package, which is the entire point of the part for CPU+GPU shared-memory inference.

Compute is exactly 3/4 of MI300X (228 vs 304 CUs; 980.6 vs 1307.4 TFLOPS FP16 dense), consistent with 6 XCDs vs 8. Memory capacity is 2/3 of MI300X. Transistor count 146B vs 153B.

TDP 550W (760W peak), about 200W below the MI300X OAM. SH5 socket rather than an OAM module; passive + active cooling.

Form-factor caveat for inference sizing: a socketed part with 128GB of coherent CPU+GPU memory can serve mid-size models without the cost of an 8-GPU platform, but it is not an OAM and cannot be assembled into a UBB Infinity Fabric mesh in the same way. 8 Infinity Fabric links at 128 GB/s are listed but the platform story differs. ROCm LLVM target gfx942.

Cross-references

Interconnect (2)