Interconnect (75)
Per-link, per-direction bandwidth and the scale-up versus scale-out distinction. Read bandwidth_basis: the repo refuses to convert a vendor bidirectional aggregate into a per-direction number without recording the derivation.
Cloud TPU7x (Ironwood) ICI (inter-chip interconnect), 3D torus, 9216-chip pod, with 6x-faster die-to-die chiplet link
600 GB/s3D TORUS, and TPU7x is the generation where the topology statement is doubled in the source: 'TPU7x chips have a direct connection to the nearest neighboring chips in 3 dimensions, resulting in a 3D mesh of networking connections' AND 'TPU7x chips have a 3D torus interconnect top…interconnect/w7c-google-tpu-ici-tpu7x
contestedmedium · 0.70
Huawei HCCS (Hierarchical Chip-to-Chip Scale)
30 GB/sPoint-to-point chip-to-chip ports, three per accelerator, giving roughly 90 GB/s of chip-to-chip bandwidth per part. No switch part is documented in the sources retrieved; the 910B systems scale out with many chips and Huawei's software stack (CANN) is what manages the collective…interconnect/huawei-hccs
contestedlow · 0.45
NVSwitch 3 (Hopper, H100/H200 - contested generation number)
450.0 GB/sSwitched, non-blocking all-to-all across the 8-GPU domain inside one server, as at NVSwitch 2 and 4. The Hopper generation's real additions are in-network compute and management rather than topology: SHARP in-network reduction and multicast, control-plane resilience, and the abil…interconnect/nvswitch-3
contestedhigh · 0.85
AWS Elastic Fabric Adapter (EFA) scale-out network
None GB/sStandard switched Ethernet data-centre network, with EFA adding the scale-out interface that carries collectives between instances and hosts. EFA is an adapter and its programming model (SRD, an OS-bypass path) is the distinguishing feature rather than any new physical layer - it…interconnect/aws-efa
draftlow · 0.40
Biren BLink die-to-die and external I/O (BR100)
None GB/sTwo distinct paths, as with several other records in this repo and easy to conflate. DIE-TO-DIE: the BR100 is a 2-die 7nm chiplet design on CoWoS packaging, the two dies joined by 896 GB/s of 'high speed die-to-die interconnect' (net2-biren-hotchips-br100) - note this is a differ…interconnect/biren-blink
draftlow · 0.45
Cambricon MLU-Link (chiplet / multi-chip scale-up)
200 GB/sChiplet-to-chiplet and chip-to-chip, used on the dual-die X4 and X8 variants. The S4 and S8 inference cards are single configurations that do not use MLU-Link for scale-up, so the two are different products in this family rather than different SKUs of one part.interconnect/cambricon-mlu-link
draftlow · 0.60
Enflame S60 fabric - VERIFIED NEGATIVE ON FIRST-PARTY ACCESS: both of Enflame's own domains, including its hardware documentation centre, return a WAF 403, so no Enflame scale-up figure can be read from the vendor
None GB/sNONE OBTAINED. Not because Enflame stated there is none, but because both of its domains block retrieval. No topology, port, link or direction could be read from any first-party source on 2026-10-05.interconnect/enflame-s60-fabric
draftmedium · 0.70
Groq LPU chip-to-chip network
None GB/sNot published. What IS published is the determinism property: because Groq statically schedules all data movement at compile time, the multi-chip topology is fixed at tapeout rather than dynamically routed, so there are no dynamic scheduling stalls and no cache misses across chip…interconnect/groq-lpu-interconnect
draftlow · 0.35
Tenstorrent Warp 100 Bridge (Wormhole in-card / adjacent-card link)
None GB/sAdjacent-card bridge, physical. The Warp 100 Bridge is a plug-in card that links two Wormhole cards installed next to each other in the same host, keyed to a specific orientation and typically pre-installed in Tenstorrent Galaxy systems. Each card supports up to two bridges. n300…interconnect/tenstorrent-warp100
draftlow · 0.50
UCIe-Advanced on-chip mesh (Rebellions Rebel100 chiplets)
125 GB/sFULL-CHIP MESH, and this is the distinguishing property. All four homogeneous chiplets of one Rebel100 are connected by a full-mesh on-chip fabric over UCIe-Advanced, so the four present to software as a single virtual die with no software-visible boundary and no I/O bottleneck -…interconnect/rebellions-ucie
draftlow · 0.55
UFI (Ultra Express Fabric)
None GB/sinterconnect/ufi-ultra-express-fabric
draftlow · 0.20
AMD Infinity Fabric (CDNA / MI100 class: 3 links, 92 GB/s bidirectional per link, 23 GT/sec, 16 lanes)
46.0 GB/sGPU-to-GPU: a hive of up to four MI100 PCIe cards, fully connected and COHERENT (AMD uses the word 'coherent' here, unlike the later PCIe-attached nodes), reached over three AMD Infinity Fabric ports per card running at 23 GT/sec. Inter-GPU links require the GPUs to sit in neighb…interconnect/amd-infinity-fabric-cdna1
verifiedhigh · 0.88
AMD Infinity Fabric (CDNA 2 / MI210 class: 3 links, 100 GB/s bidirectional per link, 25 GT/sec, 16 lanes)
50.0 GB/sGPU-to-GPU: the MI210 is a PCIe card exposing three Infinity Fabric links, reaching other GPUs through direct-connect xGMI BRIDGE CARDS in adjacent PCIe slots. AMD's CDNA 2 white paper gives both hive sizes directly: 'Dual-GPU hives: One dual-GPU hive provides up to 300 GB/s peak…interconnect/amd-infinity-fabric-cdna2-mi210
verifiedhigh · 0.90
AMD Infinity Fabric (CDNA 2 / MI250X OAM: 8 links, 100 GB/s bidirectional per link, 25 GT/sec, 16 lanes)
50.0 GB/sTWO DISTINCT FABRICS SHARE ONE LINK BUDGET, and the ROCm page is explicit that the hardware multiplexes them: 'Both interfaces can drive four AMD Infinity Fabric links. One of the AMD Infinity Fabric links of the controller at the bottom can be configured as a PCIe link.' DIE-TO-…interconnect/amd-infinity-fabric-cdna2-mi250x
verifiedhigh · 0.90
AMD Infinity Fabric (CDNA 3 / MI300X-MI325X: 7-link mesh at 32 Gbps, 128 GB/s bidirectional per link; host PCIe Gen5 x16 at 128 GB/s)
64.0 GB/sGPU-to-GPU: a FULLY CONNECTED 8-GPU mesh, not a ring. The ROCm MI300 page states 'The GPUs are using seven high-bandwidth, low-latency AMD Infinity Fabric(TM) links (red lines) to form a fully connected 8-GPU system' - seven is the minimum for 8 nodes to be mutually connected, so…interconnect/amd-infinity-fabric-cdna3
verifiedhigh · 0.90
AMD Infinity Fabric HOST / I-O path (CPU-attach and storage-networking, NOT the GPU-to-GPU fabric)
128.0 GB/sCPU/GPU attach, not a fabric. One PCIe Gen 5 x16 per GPU OAM to the host processors and to I/O devices (storage, networking). On MI300X/MI325X the node figure shows the eight OAMs reaching optional PCIe switches via retimers and HGX connectors, so host reachability can be extende…interconnect/amd-infinity-fabric-host-io-path
verifiedhigh · 0.88
AMD Infinity Fabric link (4th generation)
64 GB/sDie-to-die links inside a 3D-via Chiplet package, plus package-to-package links wiring up to 8 OAM modules into one platform. The MI325X platform integrates 8 fully connected MI325X OAM modules on an industry-standard OCP design via 4th-generation Infinity Fabric links, giving a …interconnect/amd-infinity-fabric-link
verifiedhigh · 0.85
AMD Infinity Fabric link (CDNA 4 / MI350 class)
76.8 GB/sFully connected 8-GPU node, identical to the prior generation. AMD's MI350 microarchitecture reference (net2-rocm-mi350-microarch) states 'a fully connected 8-GPU node topology, identical to the prior generation' with each GPU reaching its 7 peers over 7 Infinity Fabric links at …interconnect/amd-infinity-fabric-cdna4
verifiedhigh · 0.92
AMD Infinity Fabric scale-up link (CDNA3: 128 GB/s per direction)
128 GB/sFully connected 8-GPU mesh (each GPU connects to 7 others). No switch. 7 links per GPU for GPU-to-GPU communication. 8th link in the board spec is for scale-out (external). Scale-up bandwidth: 128 GB/s per direction per link.interconnect/amd-infinity-fabric-link-cdna3
verifiedhigh · 0.95
AMD Infinity Fabric scale-up link (CDNA4: 153.6 GB/s per direction, 20% faster)
153.6 GB/sFully connected 8-GPU mesh (each GPU connects to 7 others). No switch. 7 links per GPU for GPU-to-GPU communication. Identical topology to CDNA3. The MI355X product page lists 'Infinity Fabric Links: 7' and 'Peak Infinity Fabric Link Bandwidth: 153 GB/s' (rounded). Scale-out link…interconnect/amd-infinity-fabric-link-cdna4
verifiedhigh · 0.95
AMD xGMI (Socket/Inter-Chip Global Memory Interconnect)
50 GB/sPoint-to-point, no switch part. TWO distinct roles, and this is the part that is routinely misread: (1) DIE-TO-DIE, inside one package - on MI250X the two GCDs of one OAM module are joined by FOUR xGMI/Infinity Fabric links, which AMD gives as 4 x 25 GT/sec = 200 GB/sec peak tran…interconnect/amd-xgmi
verifiedmedium · 0.82
AWS NeuronLink (Neuron chip-to-chip scale-up)
192 GB/sNon-blocking, and AWS uses that word explicitly. Scale-up domain is one EC2 instance: Inf2 holds up to 12 Inferentia2 chips, Trn2.48xlarge holds 16 Trainium2 chips, and a Trainium2 UltraServer spans 64 chips across 4 instances. The link is chip-to-chip and bypasses the host CPU f…interconnect/aws-neuronlink
verifiedmedium · 0.75
Ayar Labs TeraPHY Optical I/O Chiplet
64 GB/sIn-package optical I/O chiplet tiled alongside compute dies via UCIe standard package electrical interface. Directly drives single-mode fibers across distances from millimeters to kilometers (package-to-package scale-up domain extension).interconnect/ayarlabs-teraphy
verifiedhigh · 0.90
Broadcom BCM78919 102.4-Tb/s CPO Switch
25 GB/sSwitched fabric with direct co-packaged optical front-panel connectivity via 512 duplex single-mode fibers. Supports arbitrary topologies including Clos, rail-optimized, rail-only, and scale-up cluster topologies up to 512 XPUs, or scale-out up to 1M+ XPUs.interconnect/broadcom-bcm78919-cpo
verifiedhigh · 0.90
Cerebras on-wafer fabric and wafer-to-wafer mesh
None GB/sOn-wafer fabric: a 2D mesh embedded in the wafer connecting the AI cores, plus HBM attached at the wafer edge - there is no off-package memory tier at all, which is the defining structural difference from every other part in this repo. SCALE-OUT IS BY ADDING WAFERS, and this is t…interconnect/cerebras-wafer-mesh
verifiedmedium · 0.70
Cloud TPU v3 ICI (inter-chip interconnect), 2D torus, 1024-chip pod
None GB/s2D TORUS across a 1024-chip pod, published as 'Interconnect topology: 2D torus'. Pod-level collectives as documented: all-reduce bandwidth per pod 340 TB/s against bisection bandwidth per pod 6.4 TB/s, a ratio of about 53. This is the same shape of result as v5e and v6e but worse…interconnect/w7c-google-tpu-ici-v3
verifiedhigh · 0.85
Cloud TPU v4 ICI (inter-chip interconnect), 3D mesh reconfigurable to 3D torus, 4096-chip pod
None GB/s3D MESH by default, RECONFIGURABLE TO A 3D TORUS - and the distinction is Google's, stated precisely, not an approximation. Google: 'v4 TPUs have a direct connection to the nearest neighboring chips in 3 dimensions, resulting in a 3D mesh of networking connections. The connection…interconnect/w7c-google-tpu-ici-v4
verifiedhigh · 0.85
Cloud TPU v5e ICI (inter-chip interconnect), 2D torus, 256-chip pod
200 GB/s2D TORUS across a 256-chip pod, per Google's own 'Interconnect topology' row. This is the part a reader planning a multi-host job will get wrong: a 2D torus is NOT a uniform mesh and its bisection bandwidth does not follow from total bandwidth by any simple division. Google publi…interconnect/w7c-google-tpu-ici-v5e
verifiedhigh · 0.90
Cloud TPU v5p ICI (inter-chip interconnect), 3D torus, 8960-chip pod
600 GB/s3D TORUS, published as 'Interconnect topology: 3D torus *'. v5p is also the generation where Google's own configuration docs say plainly that the default pod topology is NOT what a job gets: 'There are 8960 chips in a v5p Pod. The largest job that can be scheduled is a 96 cube (6…interconnect/w7c-google-tpu-ici-v5p
verifiedhigh · 0.90
Cloud TPU v6e (Trillium) ICI (inter-chip interconnect), 2D torus, 256-chip pod
400 GB/s2D TORUS across a 256-chip pod, same topology as v5e and explicitly a shared one - the v6e page states that with a 256-chip footprint per Pod, v6e shares many similarities with v5e. Google publishes the pod-level consequences as numbers, not as a derivable property: all-reduce ba…interconnect/w7c-google-tpu-ici-v6e
verifiedhigh · 0.90
Compute Express Link 2.0
63.0 GB/sPoint-to-point device attachment over PCIe PHY, extended with switching and memory pooling so a single host can reach pooled memory devices across a CXL domain.interconnect/cxl-2-0
verifiedhigh · 0.85
Compute Express Link 3.x
121.0 GB/sSwitched fabric with memory pooling and multi-host sharing across a CXL domain; peer-to-peer device-to-device traffic is possible within the domain, which is new relative to 2.0.interconnect/cxl-3-x
verifiedmedium · 0.80
Compute Express Link 4.0
242.0 GB/sSwitched fabric with pooling, now with native x2 width for platform fan-out, bundled ports combining host and Type 1/2 accelerator ports, and support for up to four retimers for channel reach.interconnect/cxl-4-0
verifiedhigh · 0.85
Google Cloud TPU Inter-Chip Interconnect (ICI)
200 GB/sSwitched mesh, NOT a full mesh, and this is the defining difference from the GPU scale-up fabrics. Per generation: v4 uses a 3D mesh that can be reconfigured into a 3D torus, with 6 interconnect links per chip, a 4096-chip pod, and optical circuit switches between cubes - the v4 …interconnect/google-tpu-ici
verifiedmedium · 0.80
HBM3 on-package memory bus
5325 GB/sOn-package, on the same interposer as the compute dies. Not a fabric - there are no cables, no switches, no topology, and no distance.interconnect/hbm3-memory-bus
verifiedhigh · 0.85
Huawei UB Link 2.0 (Ascend 950DT scale-up / unified addressing)
392.0 GB/sThree scale-up domains, and the per-NPU rate is NOT constant across them, which is the property that makes Huawei's figures easy to misread.
(1) INTRA-SERVER, 8 NPUs - Atlas 650E (14U air-cooled, ~14.5 kW, 2 x 950 CPUs, 8 x 96 GB on-chip memory = 768 GB, 4.0 TB/s peak memory ban…interconnect/huawei-ub-link
verifiedhigh · 0.85
Huawei Unified Bus (UB) — Ascend 910C / CloudMatrix 384 scale-up fabric
196.0 GB/sTwo-level switching: L1 on-board switching (7 UB Switch chips per compute node, each NPU connected to all 7 switches at 28 GB/s per port) and L2 rack-level switching (112 L2 UB switch chips across 4 communication racks, 7 sub-planes x 16 chips each, each sub-plane an independent …interconnect/huawei-ub
verifiedmedium · 0.70
Iluvatar BI-V150 / BI-V250 fabric - VERIFIED NEGATIVE: the vendor's own BI-V150 page loads and has no specification section at all, so there is no scale-up bandwidth to record
None GB/sNONE PUBLISHED. No topology, no port count, no link, no direction, no switch. There is nothing to describe, and this field is null rather than an empty string precisely so that 'the vendor told us there is no topology' stays distinguishable from 'nobody wrote the topology down'. …interconnect/iluvatar-bi-v150-and-bi-v250-fabric
verifiedmedium · 0.80
Iluvatar CoreX BI-V100 (Tiangai 100) inter-chip interconnect - 64 GB/s bidirectional, published by the vendor on the card's own interface row as 片间互联
64.0 GB/sINTER-CHIP, AIMED AT SCALE-UP, WITH NO TOPOLOGY PUBLISHED. The vendor names it 片间互联 (inter-chip interconnect) and lists it on the same interface row as a separate 'PCIe Gen4.0 x 16 lane' host link, so this 64 GB/s figure is NOT the host interface. THE HOST LINK'S OWN PUBLISHED FI…interconnect/iluvatar-bi-v100-chip-to-chip
verifiedmedium · 0.75
InfiniBand XDR (Quantum-2)
25 GB/sSwitched fat-tree with a centrally managed subnet manager providing routing and multiple paths between nodes, so simple leaf/aggregation/spine switches suffice without per-switch management.interconnect/infiniband-xdr
verifiedhigh · 0.85
Intel Gaudi 3 scale-up and scale-out fabric - 200 GbE RDMA NIC ports over 112G PAM4 SerDes; passive on-baseboard scale-up, Ethernet scale-out via the host NIC. Intel publishes no product name for it.
25.0 GB/sSCALE-UP IS A PASSIVE BASEBOARD FABRIC AND NEEDS NO SWITCH; SCALE-OUT IS ORDINARY EXTERNAL ETHERNET. The HLB-325L baseboard holds 8 Gaudi 3 OAM cards 'passively interconnected on its PCB in a non-blocking, all-to-all configuration, using 21 NICs from each card (3x 200 GbE ports t…interconnect/intel-gaudi3-roce-scaleup
verifiedhigh · 0.85
Lightmatter Passage L20 Photonic Interconnect
800 GB/sNear-Packaged Optics (NPO) on host PCB/mezzanine near ASIC, or On-Board Optics (OBO) with retimer. Interfaces to optical fabric via 32 detachable Corning CPO Flexconnect fibers.interconnect/lightmatter-passage-l20
verifiedhigh · 0.90
Marvell 6.4T Co-Packaged Optics Light Engine
800 GB/sCo-packaged optics (CPO) light engine tiles mounted immediately adjacent to compute XPU or Ethernet switch ASIC on a common substrate. Optical interfaces connect via detachable 36-fiber Metallic PIC Couplers (MPCs) to front-panel or blind-mate optical connectors.interconnect/marvell-cpo-6-4t
verifiedhigh · 0.85
MetaX MetaXLink (multi-GPU interconnect)
896.0 GB/s8-card full-interconnect topology. MetaX's C550 product page states 'MetaXLink interconnect enables an 8-card full-interconnect topology.' The C550 3D Mesh Supernode supports up to 8 servers and 64 cards with 3D Mesh topology. No switch part is named.interconnect/metaxlink
verifiedmedium · 0.75
Moore Threads MTLink (MTT S4000 card-to-card fabric)
120.0 GB/sPhysical card-to-card links via an MTLink Bridge accessory. The S4000 page states the MTLink Bridge supports 2-, 4- and 8-card topologies, which is a small direct-attached domain comparable to the 8-way meshes AMD's Infinity Fabric provides and smaller than what NVSwitch reaches.…interconnect/moore-threads-mtlink
verifiedmedium · 0.65
NVIDIA BlueField-3 DPU
50 GB/sStandard Ethernet or InfiniBand switched fabric. BlueField-3 can operate in either Ethernet or InfiniBand mode.interconnect/nic-bluefield3-dpu
verifiedhigh · 0.90
NVIDIA BlueField-4 DPU
100 GB/sStandard Ethernet or InfiniBand switched fabric.interconnect/nic-bluefield4-dpu
verifiedhigh · 0.85
NVIDIA ConnectX-7 NDR 400Gb/s InfiniBand HCA
50 GB/sSwitched fat-tree or Dragonfly+ via Quantum-2 switches. ConnectX-7 is the adapter (HCA) endpoint.interconnect/nic-connectx7-ndr-400gbps
verifiedhigh · 0.92
NVIDIA ConnectX-8 XDR 800Gb/s InfiniBand SuperNIC
100 GB/sSwitched fat-tree or Dragonfly+ via Quantum-X800 switches. ConnectX-8 is the SuperNIC endpoint.interconnect/nic-connectx8-xdr-800gbps
verifiedhigh · 0.88
NVIDIA NVLink 2.0
25 GB/sDirect point-to-point links between GPU pairs, partial mesh. NVIDIA's Volta datasheet states 'Up to eight V100 accelerators can be interconnected', so 8 GPUs is the practical all-to-all ceiling and it is reached by direct links alone - there is no switch generation below NVSwitch…interconnect/nvlink-2
verifiedhigh · 0.85
NVIDIA NVLink 3.0
25 GB/sDirect point-to-point links between GPU pairs. All-to-all full mesh is only practical up to 8 GPUs; beyond that, NVSwitch is required to avoid partial connectivity.interconnect/nvlink-3
verifiedhigh · 0.90
NVIDIA NVLink 4.0
25 GB/sPoint-to-point GPU-to-GPU links, exposed on both sides of the card (NVLink bridge on PCIe SKUs such as H100 NVL, direct in SXM/ HGX baseboards). Switched via NVSwitch 4 for a non-blocking 8-GPU server domain.interconnect/nvlink-4
verifiedhigh · 0.92
NVIDIA NVLink 5.0
50 GB/sDirect GPU-to-GPU links on the device, plus switch trays that extend NVLink into a 72-GPU NVLink domain (GB200/GB300 NVL72).interconnect/nvlink-5
verifiedhigh · 0.90
NVIDIA NVLink 6.0
41.7 GB/sDirect GPU-to-GPU links plus switch fabric; Vera Rubin NVL72 connects 72 GPUs all-to-all as one non-blocking compute fabric.interconnect/nvlink-6
verifiedhigh · 0.90
NVIDIA NVLink Switch 2
300 GB/sSwitched, non-blocking within the domain. NVIDIA's HGX A100 table shows NVSwitch absent at 4 GPUs ('N/A') and present at 8 and 16, with the per-GPU rate unchanged at 600 GB/s aggregate across all three sizes - i.e. the switch changes the domain size and removes the mesh topology …interconnect/nvswitch-2
verifiedhigh · 0.85
NVIDIA NVLink Switch 4
450 GB/sSwitched, non-blocking all-to-all across an 8-GPU domain inside one server. Every GPU reaches every other GPU at full NVLink rate simultaneously.interconnect/nvswitch-4
verifiedhigh · 0.92
NVIDIA NVLink Switch 5
900 GB/sSwitched non-blocking fabric supporting both 8-GPU and 72-GPU NVLink domains (GB200/GB300 NVL72).interconnect/nvswitch-5
verifiedhigh · 0.88
NVIDIA NVLink-C2C (second generation)
900 GB/sPoint-to-point die-to-die chip-to-chip link. Integrates at PCB level, in a multi-chip module, or across a silicon interposer / wafer-level connection. One such link joins a Grace CPU to a Hopper GPU (GH200), two Grace CPUs to each other, or two Blackwell GPUs plus a Grace CPU in …interconnect/nvlink-c2c
verifiedhigh · 0.90
NVIDIA Quantum-2 InfiniBand Switch
50 GB/sFat-tree, Dragonfly+, multi-dimensional torus. 1U fixed-configuration switch.interconnect/nic-quantum2-switch
verifiedhigh · 0.92
NVIDIA Quantum-X800 InfiniBand Switch
100 GB/sFat-tree, Dragonfly+. 1U fixed-configuration switch.interconnect/nic-quantumx800-switch
verifiedhigh · 0.88
NVIDIA Spectrum-X Ethernet Platform
100 GB/sLeaf-spine Ethernet. Spectrum-X Multiplane scales to 128K GPUs in two tiers.interconnect/nic-spectrumx-ethernet
verifiedhigh · 0.85
NVLink 1 (Pascal, Tesla P100)
20.0 GB/sDirect point-to-point links between GPU pairs. With 4 links per GPU an all-to-all mesh is impractical beyond a few GPUs: NVIDIA's own P100 material shows the 8-GPU node as 'up to eight Tesla P100 GPUs interconnected in a single node', reached by grouping the limited links per pee…interconnect/nvlink-1
verifiedhigh · 0.90
NVSwitch 1 (Volta, DGX-2 / HGX-2)
150.0 GB/sSwitched, non-blocking all-to-all crossbar. The NVLink crossbar reaches 1.98 TB/s of bisection bandwidth at 80% NVLink efficiency (net2-nvidia-nvswitch1-dgx2-blog), so the switch is not the bandwidth limit - the links are. Domain size is the switch's contribution: DGX-2 holds 16 …interconnect/nvswitch-1
verifiedhigh · 0.90
PCI Express 1.0
4.0 GB/sPoint-to-point host-to-device (root complex to endpoint), up to 16 lanes. Becomes a shared fabric only via PCIe switches or host bridges.interconnect/pcie-gen1
verifiedhigh · 0.90
PCI Express 2.0
8.0 GB/sPoint-to-point host-to-device (root complex to endpoint), up to 16 lanes. Becomes a shared fabric only via PCIe switches or host bridges.interconnect/pcie-gen2
verifiedhigh · 0.90
PCI Express 3.0
15.75 GB/sPoint-to-point host-to-device (root complex to endpoint), up to 16 lanes. Becomes a shared fabric only via PCIe switches or host bridges.interconnect/pcie-gen3
verifiedhigh · 0.90
PCI Express 4.0
31.5 GB/sPoint-to-point host-to-device (root complex to endpoint), up to 16 lanes. Becomes a shared fabric only via PCIe switches or host bridges.interconnect/pcie-gen4
verifiedhigh · 0.92
PCI Express 5.0
63.0 GB/sPoint-to-point host-to-device by default (root complex to endpoint), up to 16 lanes. Becomes a shared fabric only through PCIe switches or host bridges, in which case ordering and oversubscription apply.interconnect/pcie-gen5
verifiedhigh · 0.92
PCI Express 6.0
121.0 GB/sPoint-to-point host-to-device, up to 16 lanes, with flit-level framing and signalling changes versus PCIe 5.0. Shares the physical layer with CXL 4.0. PCI-SIG publishes link widths of 1, 2, 4, 8, 12, 16 and 32 (w7p-pcisig-pcie5-faq-verified); x16 is used here for comparability, n…interconnect/pcie-gen6
verifiedhigh · 0.85
PCI Express 7.0
242.0 GB/sPoint-to-point host-to-device, up to 16 lanes, with flit-level framing and PAM4 signalling as PCIe 6.0. PCI-SIG publishes link widths of 1, 2, 4, 8, 12, 16 and 32 (w7p-pcisig-pcie5-faq-verified); x16 is used here for comparability across the pcie-gen* family, not because it is th…interconnect/pcie-gen7
verifiedhigh · 0.85
PCIe Gen5 x16 host link (128 GB/s, unchanged across CDNA3/CDNA4)
128 GB/sHost-to-GPU (tree topology via root complex). Each GPU has one PCIe Gen5 x16 link to the host. In a dual-socket 8-GPU system, 4 GPUs are connected to each socket's root complex.interconnect/amd-pcie-gen5-x16
verifiedhigh · 0.95
RoCE (RDMA over Converged Ethernet)
None GB/sAny Ethernet topology that can carry lossless RDMA - typically a leaf-spine fabric, but constrained by the requirement for lossless operation (PFC / priority flow control, DCB) and typically single-path rather than multi-path. Contrast with InfiniBand, which gets losslessness and…interconnect/roce
verifiedmedium · 0.80
Tenstorrent QSFP-DD fabric (Wormhole 200G, Blackhole 800G)
25 GB/sStandard switched Ethernet ports on each card, daisy-chained into racks rather than switched into one large non-blocking domain. Wormhole: 2x QSFP-DD 200G plus 2x Warp 100 Bridge connectors per card. Blackhole: 4x QSFP-DD 800G passive per card, and the in-card Warp bridges are go…interconnect/tenstorrent-qsfp-dd
verifiedmedium · 0.72
UALink 200G 1.0
25 GB/sMulti-layer fabric (UPLI protocol / transaction / data link / physical). Consortium-supported topologies: mesh and ring for small clusters of 4-16 nodes, torus for mid-scale, SWITCHED POD as the primary deployment model scaling to hundreds or thousands of accelerators, and direct…interconnect/ualink-200g-1-0
verifiedmedium · 0.78
Ultra Ethernet (UEC) and Ethernet scale-out baseline
None GB/sSwitched Ethernet, classically leaf-spine. UEC's design goal is precisely to keep this topology while fixing the collective-communication behaviour that makes commodity Ethernet awkward for AI.interconnect/ethernet-uec
verifiedmedium · 0.80
Most referenced
The records other records point at. Useful as an entry point: a heavily referenced accelerator or engine is one many decisions in this repo assume.
| Record | Referenced by | Cites |
|---|---|---|
| PCI Express 4.0 | 1332 | 6 |
| PCI Express 5.0 | 493 | 7 |
| PCI Express 3.0 | 157 | 3 |
| NVIDIA NVLink 4.0 | 48 | 4 |
| AMD Infinity Fabric link (4th generation) | 38 | 4 |
| AMD xGMI (Socket/Inter-Chip Global Memory Interconnect) | 35 | 5 |
| NVIDIA NVLink Switch 4 | 32 | 2 |
| NVIDIA NVLink 3.0 | 28 | 4 |