inference/research
verifiedhigh · 0.85updated 2026-10-05

AMD Instinct MI350P

amd CDNA4 (gfx950) 2025

Fields

id
accelerators/amd-instinct-mi350p
Vendor
amd
Architecture
CDNA4 (gfx950)
Release year
2025
Process (nm)
3
Form factors
pcie
VRAM (GB)
144
Memory type
hbm3e
Memory bus (bit)
4,096
Memory bandwidth (GB/s)
4,000
Bandwidth basis
'4 TB/s' per the AMD spec table on a 4096-bit interface - exactly half the 8192-bit MI350X/MI355X, with correspondingly half the memory (144GB vs 288GB). The page gives no memory-clock figure for this part, so the 4 TB/s is a vendor figure without published arithmetic. AUDIT CORRECTION: 4096-bit x 8 Gb/s per pin / 8 = 4,096 GB/s, not 4,000. The correct per-pin rate is 7.81 Gbps (4000 x 8 / 4096). (The generic 'HBM3E = 5.0 Gbps' assumption that a mechanical audit would apply gives 2,560 GB/s and is wrong for this part: MI350-series HBM3E runs at ~7.81 Gbps per pin, and AMD's own spec table lists 'Memory Clock 8 GHz'.)
On-chip cache
[object Object]
Peak FLOPS
precisionfp32tflops72denseyesvendor_claimyessource_idamd-mi350p-product-pagebasisvendor-spec-sheetbasis_detailTranscribed from the vendor's own fp32 for AMD Instinct MI350P (source of record: 'AMD Instinct MI350P PCIe cards product page', kind: spec-sheet). Recorded dense:true as printed.precisionfp16tflops72denseyesvendor_claimyessource_idamd-mi350p-product-pagenotesVECTOR FP16 ('Peak Half Precision (FP16) Performance 72 TFLOPs'). No sparsity variant, dense. NOTE the record also has an fp16 72.0 row that is the VECTOR path while the second fp16 row (1150) is the MATRIX path - on this part vector is 16x slower than matrix, so a naive reader taking 'the' FP16 number for this card would be off by 16x in either direction.basisvendor-spec-sheetbasis_detailTranscribed from the vendor's own fp16 for AMD Instinct MI350P (source of record: 'AMD Instinct MI350P PCIe cards product page', kind: spec-sheet). Recorded dense:true as printed. Full reasoning for this row retained verbatim in notes.precisionfp16tflops1,150denseyesvendor_claimyessource_idamd-mi350p-product-pagebasisvendor-spec-sheetbasis_detailTranscribed from the vendor's own fp16 for AMD Instinct MI350P (source of record: 'AMD Instinct MI350P PCIe cards product page', kind: spec-sheet). Recorded dense:true as printed.precisionfp16tflops2,300densenovendor_claimyessource_idamd-mi350p-product-pagebasisvendor-spec-sheetbasis_detailTranscribed from the vendor's own fp16 for AMD Instinct MI350P (source of record: 'AMD Instinct MI350P PCIe cards product page', kind: spec-sheet). Recorded dense:false - the vendor prints this as a structured-sparsity figure; the dense companion row on this record is the halved value. See this record's notes for the sparsity-footnote rule.precisionbf16tflops1,150denseyesvendor_claimyessource_idamd-mi350p-product-pagebasisvendor-spec-sheetbasis_detailTranscribed from the vendor's own bf16 for AMD Instinct MI350P (source of record: 'AMD Instinct MI350P PCIe cards product page', kind: spec-sheet). Recorded dense:true as printed.precisionbf16tflops2,300densenovendor_claimyessource_idamd-mi350p-product-pagebasisvendor-spec-sheetbasis_detailTranscribed from the vendor's own bf16 for AMD Instinct MI350P (source of record: 'AMD Instinct MI350P PCIe cards product page', kind: spec-sheet). Recorded dense:false - the vendor prints this as a structured-sparsity figure; the dense companion row on this record is the halved value. See this record's notes for the sparsity-footnote rule.precisionfp8tflops2,300denseyesvendor_claimyessource_idamd-mi350p-product-pagenotesAMD MI350P page: 'Peak Open Compute Project Eight-bit Precision Matrix (OCP-FP8) Performance 2.3 PFLOPs' DENSE, with 'with Structured Sparsity' 4.6 PFLOPs as the separate sparse row (stored separately here with dense:false).basisvendor-spec-sheetbasis_detailTranscribed from the vendor's own fp8 for AMD Instinct MI350P (source of record: 'AMD Instinct MI350P PCIe cards product page', kind: spec-sheet). Recorded dense:true as printed. Full reasoning for this row retained verbatim in notes.precisionfp8tflops4,600densenovendor_claimyessource_idamd-mi350p-product-pagebasisvendor-spec-sheetbasis_detailTranscribed from the vendor's own fp8 for AMD Instinct MI350P (source of record: 'AMD Instinct MI350P PCIe cards product page', kind: spec-sheet). Recorded dense:false - the vendor prints this as a structured-sparsity figure; the dense companion row on this record is the halved value. See this record's notes for the sparsity-footnote rule.precisionfp6tflops4,600denseyesvendor_claimyessource_idamd-mi350p-product-pagenotesAMD MI350P page: 'Peak Microscaling Six-bit Precision Matrix (MXFP6) Performance 4.6 PFLOPs' - NO 'with Structured Sparsity' row, so DENSE. Exactly half the MI350X's 9.2, consistent with this part having half the memory interface (4096-bit vs 8192-bit) and half the matrix cores per package.basisvendor-spec-sheetbasis_detailTranscribed from the vendor's own fp6 for AMD Instinct MI350P (source of record: 'AMD Instinct MI350P PCIe cards product page', kind: spec-sheet). Recorded dense:true as printed. Full reasoning for this row retained verbatim in notes.precisionfp4tflops4,600denseyesvendor_claimyessource_idamd-mi350p-product-pagenotesAMD MI350P page: 'Peak Microscaling Four-bit Precision Matrix (MXFP4) Performance 4.6 PFLOPs' - no sparsity variant, so DENSE. Same throughput as MXFP6 on this part.basisvendor-spec-sheetbasis_detailTranscribed from the vendor's own fp4 for AMD Instinct MI350P (source of record: 'AMD Instinct MI350P PCIe cards product page', kind: spec-sheet). Recorded dense:true as printed. Full reasoning for this row retained verbatim in notes.precisionint8tflops2,300denseyesvendor_claimyessource_idamd-mi350p-product-pagebasisvendor-spec-sheetbasis_detailTranscribed from the vendor's own int8 for AMD Instinct MI350P (source of record: 'AMD Instinct MI350P PCIe cards product page', kind: spec-sheet). Recorded dense:true as printed.precisionint8tflops4,600densenovendor_claimyessource_idamd-mi350p-product-pagebasisvendor-spec-sheetbasis_detailTranscribed from the vendor's own int8 for AMD Instinct MI350P (source of record: 'AMD Instinct MI350P PCIe cards product page', kind: spec-sheet). Recorded dense:false - the vendor prints this as a structured-sparsity figure; the dense companion row on this record is the halved value. See this record's notes for the sparsity-footnote rule.precisionfp64tflops36denseyesvendor_claimyessource_idamd-mi350p-product-pagenotesAUDIT 2026-10-04: ROW ADDED, not corrected - FP64 was absent entirely. AMD's spec table prints 'Peak Double Precision (FP64) Performance 36.0 TFLOPs' and 'Peak Double Precision Matrix (FP64) Performance 36.0 TFLOPs' (vector and matrix paths identical on CDNA4). Recorded dense:true: AMD annotates sparsity only on rows it explicitly titles 'with Structured Sparsity' (FP8, FP16, BF16, INT8), and FP64 has no such row on any MI350-series page. Ratio check confirms the derivation: MI350X 72.1 and MI350P 36.0 are each exactly half MI355X's 78.6, matching the halved-XCD relationship between the parts (MI355X 8 XCDs at 2400 MHz, MI350X and MI350P 4 XCDs at 2200 MHz). This schema's precision enum has no fp64 member, hence precision 'other'.basisvendor-spec-sheetbasis_detailMI350P product page, 'Peak Double Precision (FP64) Performance 36.0 TFLOPs'. Exactly half MI350X's 72.1.
TDP (W)
600
Unified memory
no
Consumer part
no
notes
AUDIT 2026-10-03 (AMD convention re-verified against the MI350P page; no values changed): the MI350P page uses the identical labelling scheme as the MI350X - 'Peak X Performance' DENSE, 'Peak X Performance with Structured Sparsity' SPARSE at 2x - so every dense flag here is correct. Same micro-scaling caveat as the MI350X: the MXFP4 and MXFP6 rows print 4.6 PFLOPs with NO sparsity variant and are therefore dense, not sparse-and-not-to-be-halved. This page also prints the vector-vs-matrix split explicitly ('Peak Half Precision (FP16) Performance 72 TFLOPs' against 'Peak Half Precision Matrix (FP16) Performance 1.15 PFLOPs'), and the record's two fp16 rows are those two different paths - 72.0 vector and 1150 matrix - now annotated so they cannot be read as a contradiction. THE POINT OF THIS PART for inference: it is the only CDNA4 part with a 4096-bit interface and a PCIe add-in-card form factor ('PCIe Add-in Card', 'Dimensions Full Height / Double Slot', 600W TBP configurable to 450W), i.e. it is the air-cooled, rack-optional MI350 member. Its 4 TB/s and 144 GB are exactly half the MI350X's 8 TB/s and 288 GB, and its dense matrix throughput is exactly half too - but it needs no OAM baseboard, which is often the binding constraint. The CDNA4 part you can actually buy as a normal add-in card, and the only CDNA4 SKU without an OAM/8-GPU-platform story. Exactly HALF of an OAM part in every dimension: 128 CUs vs 256, 8192 SPs vs 16,384, 512 matrix cores vs 1024, 73B transistors vs 185B, 144 GB vs 288 GB, 4096-bit vs 8192-bit, 4 TB/s vs 8 TB/s, 128 MB Infinity Cache vs 256 MB. Note the page does NOT state a release year for MI350P (no 'Launch Date' field), so release_year 2025 is inferred from it shipping alongside the June 2025 MI350 series - treat it as approximate. Power is the interesting part: 600W max TBP but 450W TBP is configurable, and the card uses a standard 12V-2x6 connector rather than a 54V UBB. That makes it deployable in ordinary air-cooled servers. Passive cooling, full height / 267mm / double slot, Linux x86_64 only. No Infinity Fabric links are listed on the spec page - scale-up beyond the card is PCIe only. That is a real limitation for multi-GPU inference: the OAM parts get a 153 GB/s scale-up mesh, this card gets PCIe Gen5 x16 (128 GB/s bidirectional) per card. CDNA4 software surface is confirmed on the product page: OpenMP, OpenCL, HIP, ROCm, TensorFlow, PyTorch, ONNX-RT, SGLang, JAX, Triton, Kokkos, RAJA. That is the broadest explicitly-listed framework support of any part here and worth noting for inference engine selection. TF32 is software-emulated on CDNA4. Sparse figures are 2x dense. Two fp16 entries on purpose: 72 TFLOPS vector, 1150 TFLOPS matrix. MXFP6/MXFP4 at 4600 PFLOPs. ROCm LLVM target gfx950. FP64 (AUDIT 2026-10-04, row added): 36.0 TFLOPs, vector and matrix both, dense. Recorded on the sibling nvidia-b200 comparison as AMD's 2x-B200 HPC pitch: AMD's chart plots MI350X FP64 72.1 vs B200 SXM 5's 37. ON-CHIP CACHE ROW ADDED 2026-10-05 (schema authority pass, agent w5-schema) - corrected to 2026-10-05 below. `onchip_cache` is new in schemas/accelerator.schema.json. This figure was already stated in these notes and was unqueryable; the schema field exists so it can be filtered and compared instead of grepped. The value was verified against the first-party source named in `source_note`, and the trap that source contains is recorded there too. NO new number was introduced: every value below was already present in this record's own prose.

Notes

AUDIT 2026-10-03 (AMD convention re-verified against the MI350P page; no values changed): the MI350P page uses the identical labelling scheme as the MI350X - 'Peak X Performance' DENSE, 'Peak X Performance with Structured Sparsity' SPARSE at 2x - so every dense flag here is correct. Same micro-scaling caveat as the MI350X: the MXFP4 and MXFP6 rows print 4.6 PFLOPs with NO sparsity variant and are therefore dense, not sparse-and-not-to-be-halved. This page also prints the vector-vs-matrix split explicitly ('Peak Half Precision (FP16) Performance 72 TFLOPs' against 'Peak Half Precision Matrix (FP16) Performance 1.15 PFLOPs'), and the record's two fp16 rows are those two different paths - 72.0 vector and 1150 matrix - now annotated so they cannot be read as a contradiction. THE POINT OF THIS PART for inference: it is the only CDNA4 part with a 4096-bit interface and a PCIe add-in-card form factor ('PCIe Add-in Card', 'Dimensions Full Height / Double Slot', 600W TBP configurable to 450W), i.e. it is the air-cooled, rack-optional MI350 member. Its 4 TB/s and 144 GB are exactly half the MI350X's 8 TB/s and 288 GB, and its dense matrix throughput is exactly half too - but it needs no OAM baseboard, which is often the binding constraint. The CDNA4 part you can actually buy as a normal add-in card, and the only CDNA4 SKU without an OAM/8-GPU-platform story. Exactly HALF of an OAM part in every dimension: 128 CUs vs 256, 8192 SPs vs 16,384, 512 matrix cores vs 1024, 73B transistors vs 185B, 144 GB vs 288 GB, 4096-bit vs 8192-bit, 4 TB/s vs 8 TB/s, 128 MB Infinity Cache vs 256 MB.

Note the page does NOT state a release year for MI350P (no 'Launch Date' field), so release_year 2025 is inferred from it shipping alongside the June 2025 MI350 series - treat it as approximate.

Power is the interesting part: 600W max TBP but 450W TBP is configurable, and the card uses a standard 12V-2x6 connector rather than a 54V UBB. That makes it deployable in ordinary air-cooled servers. Passive cooling, full height / 267mm / double slot, Linux x86_64 only.

No Infinity Fabric links are listed on the spec page - scale-up beyond the card is PCIe only. That is a real limitation for multi-GPU inference: the OAM parts get a 153 GB/s scale-up mesh, this card gets PCIe Gen5 x16 (128 GB/s bidirectional) per card.

CDNA4 software surface is confirmed on the product page: OpenMP, OpenCL, HIP, ROCm, TensorFlow, PyTorch, ONNX-RT, SGLang, JAX, Triton, Kokkos, RAJA. That is the broadest explicitly-listed framework support of any part here and worth noting for inference engine selection.

TF32 is software-emulated on CDNA4. Sparse figures are 2x dense. Two fp16 entries on purpose: 72 TFLOPS vector, 1150 TFLOPS matrix. MXFP6/MXFP4 at 4600 PFLOPs. ROCm LLVM target gfx950. FP64 (AUDIT 2026-10-04, row added): 36.0 TFLOPs, vector and matrix both, dense. Recorded on the sibling nvidia-b200 comparison as AMD's 2x-B200 HPC pitch: AMD's chart plots MI350X FP64 72.1 vs B200 SXM 5's 37.

ON-CHIP CACHE ROW ADDED 2026-10-05 (schema authority pass, agent w5-schema) - corrected to 2026-10-05 below. `onchip_cache` is new in schemas/accelerator.schema.json. This figure was already stated in these notes and was unqueryable; the schema field exists so it can be filtered and compared instead of grepped. The value was verified against the first-party source named in `source_note`, and the trap that source contains is recorded there too. NO new number was introduced: every value below was already present in this record's own prose.

Cross-references

Interconnect (1)