inference/research
verifiedhigh · 0.85updated 2026-10-08

AWS Trainium3

amazon NeuronCore-v4 (8 cores per chip) 2025

Fields

id
accelerators/aws-trainium3
Vendor
amazon
Architecture
NeuronCore-v4 (8 cores per chip)
Release year
2025
Process (nm)
3
Form factors
oam
VRAM (GB)
144
Memory type
hbm3e
Memory bandwidth (GB/s)
4,900
Bandwidth basis
Vendor-published per-chip figure: 144 GiB HBM3e at 4.9 TB/s (Neuron docs and EC2 Trn3 page both state this directly). Trn3 UltraServer aggregates to 706 TB/s across 144 chips.
Peak FLOPS
precisionfp8tflops2,517denseyesvendor_claimyessource_idaws-trainium3-architecture-neuron-docsnotes2,517 MXFP8/MXFP4 TFLOPS dense. The Neuron docs list this as 'MXFP8/MXFP4 TFLOPS' — the same figure covers both precisions. The EC2 Trn3 page rounds to '362 MXFP8 PFLOPs' for the 144-chip UltraServer (362,000 / 144 ≈ 2,514 per chip, consistent with 2,517).basisvendor-docsbasis_detailAWS Neuron SDK architecture documentation (a docs page, filed as kind blog in the source record). Official AWS documentation.precisionbf16tflops671denseyesvendor_claimyessource_idaws-trainium3-architecture-neuron-docsnotes671 BF16/FP16/TF32 TFLOPS dense. The Neuron docs list '671 BF16/FP16/TF32 TFLOPS' as a single row covering all three precisions.basisvendor-docsbasis_detailAWS Neuron SDK architecture documentation (a docs page, filed as kind blog in the source record). Official AWS documentation.precisionfp16tflops2,517densenovendor_claimyessource_idaws-trainium3-architecture-neuron-docsnotes2,517 FP16/BF16/TF32 sparse TFLOPS. The Neuron docs list this as a separate row from the dense 671 figure, indicating 2:4 structured sparsity. This is the ONLY sparse figure published for Trainium3.basisvendor-docsbasis_detailAWS Neuron SDK architecture documentation (a docs page, filed as kind blog in the source record). Official AWS documentation.precisionfp32tflops183denseyesvendor_claimyessource_idaws-trainium3-architecture-neuron-docsnotes183 FP32 TFLOPS dense.basisvendor-docsbasis_detailAWS Neuron SDK architecture documentation (a docs page, filed as kind blog in the source record). Official AWS documentation.
Unified memory
no
Consumer part
no
notes
Trainium3 is AWS's fourth-generation AI chip and first 3nm accelerator. GA announced December 2025 at re:Invent; Amazon Bedrock is already serving production workloads on it. KEY NEURON COMPILER CONSTRAINTS (same as Trainium2, per alt-neuron-compiler source): (1) neuronx-cc auto-casts FP32 to BF16 at compile time — FP32 models are silently downcast, changing effective throughput without changing the peak number. (2) The compiler outputs NEFF (Neuron Executable Format), a proprietary intermediate format — models must be compiled for Trainium and cannot run on other hardware without recompilation. (3) Logical NeuronCore Configuration (LNC) lets multiple physical NeuronCores be combined into one logical core for sharding. ARCHITECTURE: 8 NeuronCore-v4 cores per chip, 16 CC-Cores for collective communication, 256 MiB SBUF (on-chip SRAM), NeuronLink-v4 at 2.56 TB/s per device (2x Trainium2). NeuronSwitch-v1 is an all-to-all fabric that doubles interchip bandwidth over Trn2. Trainium3 supports dynamic shapes and control flow via ISA extensions — a first for the Trainium line. Built-in collective communication engines accelerate synchronization for large transformer, diffusion, and MoE models. Trn3 UltraServers scale to 144 chips in EC2 UltraClusters 3.0 with hundreds of thousands of chips in a single non-blocking petabit-scale network. TDP is not published. Process node is 3nm (TSMC). The 4.4x performance improvement over Trn2 is a vendor claim comparing Trn3 UltraServer to Trn2 UltraServer at the system level, not per-chip. MEMORY_BUS_WIDTH: STILL NULL, AND HERE IS PRECISELY WHAT WAS LOOKED FOR (2026-10-04). The vendor publishes NO memory-bus width for this part, and none was back-computed from the published bandwidth. NO FIGURE WAS BACK-COMPUTED FROM BANDWIDTH.[REPAIRED 2026-10-08 by w8-reverify. This sentence previously read '(2026-10-04). %s NO FIGURE WAS BACK-COMPUTED FROM BANDWIDTH' — a literal printf placeholder left in the JSON by the wave-3 pass (commit 9968769) across 34 accelerator records, and invisible to every check in this repo because validate.py never reads notes. The substitution text is the same boilerplate the 7 uncorrupted records in this family already carry, and it is only valid here because memory_bus_bit is null on every one of the 34, so "the vendor does not publish it" is the true state. A record with a non-null memory_bus_bit must NOT receive this filler.] That is the standing rule for this field in this repo and it was applied to every null here rather than to a subset: a width derived by dividing a published aggregate bandwidth by an assumed or half-assumed per-pin rate is two inferences stacked on one number, and if either inference is wrong the record looks populated while being wrong. The correct state of this field is 'the vendor does not publish it', and the note above names the specific document that was read and found not to carry it, so a future pass does not have to re-establish that from scratch. MEMORY_BUS_WIDTH: STILL NULL, AND HERE IS PRECISELY WHAT WAS LOOKED FOR (2026-10-04). AWS publishes no memory-bus width for Inferentia or Trainium. The Neuron hardware documentation and the EC2 instance-type pages give capacity and aggregate bandwidth only. Not back-computed: Trainium2's published figure is a per-instance aggregate across a 16-chip pod, not a per-chip number, so dividing it by chip count yields a pod figure rather than a bus width. NO FIGURE WAS BACK-COMPUTED FROM BANDWIDTH. That is the standing rule for this field in this repo and it was applied to every null here rather than to a subset: a width derived by dividing a published aggregate bandwidth by an assumed or half-assumed per-pin rate is two inferences stacked on one number, and if either is wrong the record looks populated while being wrong. The correct state of this field is 'the vendor does not publish it', and the text above names the specific document read and found not to carry it, so a future pass does not have to re-establish that from scratch.

Notes

Trainium3 is AWS's fourth-generation AI chip and first 3nm accelerator. GA announced December 2025 at re:Invent; Amazon Bedrock is already serving production workloads on it. KEY NEURON COMPILER CONSTRAINTS (same as Trainium2, per alt-neuron-compiler source): (1) neuronx-cc auto-casts FP32 to BF16 at compile time — FP32 models are silently downcast, changing effective throughput without changing the peak number. (2) The compiler outputs NEFF (Neuron Executable Format), a proprietary intermediate format — models must be compiled for Trainium and cannot run on other hardware without recompilation. (3) Logical NeuronCore Configuration (LNC) lets multiple physical NeuronCores be combined into one logical core for sharding. ARCHITECTURE: 8 NeuronCore-v4 cores per chip, 16 CC-Cores for collective communication, 256 MiB SBUF (on-chip SRAM), NeuronLink-v4 at 2.56 TB/s per device (2x Trainium2). NeuronSwitch-v1 is an all-to-all fabric that doubles interchip bandwidth over Trn2. Trainium3 supports dynamic shapes and control flow via ISA extensions — a first for the Trainium line. Built-in collective communication engines accelerate synchronization for large transformer, diffusion, and MoE models. Trn3 UltraServers scale to 144 chips in EC2 UltraClusters 3.0 with hundreds of thousands of chips in a single non-blocking petabit-scale network. TDP is not published. Process node is 3nm (TSMC). The 4.4x performance improvement over Trn2 is a vendor claim comparing Trn3 UltraServer to Trn2 UltraServer at the system level, not per-chip. MEMORY_BUS_WIDTH: STILL NULL, AND HERE IS PRECISELY WHAT WAS LOOKED FOR (2026-10-04). The vendor publishes NO memory-bus width for this part, and none was back-computed from the published bandwidth. NO FIGURE WAS BACK-COMPUTED FROM BANDWIDTH.[REPAIRED 2026-10-08 by w8-reverify. This sentence previously read '(2026-10-04). %s NO FIGURE WAS BACK-COMPUTED FROM BANDWIDTH' — a literal printf placeholder left in the JSON by the wave-3 pass (commit 9968769) across 34 accelerator records, and invisible to every check in this repo because validate.py never reads notes. The substitution text is the same boilerplate the 7 uncorrupted records in this family already carry, and it is only valid here because memory_bus_bit is null on every one of the 34, so "the vendor does not publish it" is the true state. A record with a non-null memory_bus_bit must NOT receive this filler.] That is the standing rule for this field in this repo and it was applied to every null here rather than to a subset: a width derived by dividing a published aggregate bandwidth by an assumed or half-assumed per-pin rate is two inferences stacked on one number, and if either inference is wrong the record looks populated while being wrong. The correct state of this field is 'the vendor does not publish it', and the note above names the specific document that was read and found not to carry it, so a future pass does not have to re-establish that from scratch.

MEMORY_BUS_WIDTH: STILL NULL, AND HERE IS PRECISELY WHAT WAS LOOKED FOR (2026-10-04). AWS publishes no memory-bus width for Inferentia or Trainium. The Neuron hardware documentation and the EC2 instance-type pages give capacity and aggregate bandwidth only. Not back-computed: Trainium2's published figure is a per-instance aggregate across a 16-chip pod, not a per-chip number, so dividing it by chip count yields a pod figure rather than a bus width. NO FIGURE WAS BACK-COMPUTED FROM BANDWIDTH. That is the standing rule for this field in this repo and it was applied to every null here rather than to a subset: a width derived by dividing a published aggregate bandwidth by an assumed or half-assumed per-pin rate is two inferences stacked on one number, and if either is wrong the record looks populated while being wrong. The correct state of this field is 'the vendor does not publish it', and the text above names the specific document read and found not to carry it, so a future pass does not have to re-establish that from scratch.

Cross-references

Interconnect (2)