Biren BR104 GPGPU (single-die inference accelerator)

None available. The BR104 is described as the 'half-size sibling of the BR100 for inference workloads' with 32 GB HBM2e at 300 W TDP, but no memory bandwidth figure is published in any source located. The BR100's 1.6 TB/s cannot be halved to derive the BR104's bandwidth because the memory subsystem may not be a simple halving.

THE HIERARCHY POINT: the BR104 is the inference-oriented sibling of the BR100, with half the memory (32 GB vs 64 GB) and roughly half the TDP (300 W vs 550 W). It is a single-die part, not a 2-die chiplet like the BR100. The BR104 shipped in place of the BR100 after TSMC halted all Biren manufacturing in October 2022 and Biren was added to the BIS Entity List in October 2023. The BR104 uses the BIRENSUPA software stack. No compute throughput figures are published for the BR104 in any source located — the BR100's 1024 TFLOPS BF16 / 2048 TOPS INT8 are 2020 launch-release figures for a different part and must not be carried over. The BR104 is significant because it represents Biren's pivot from a training-focused part (BR100) to an inference-focused part (BR104) under supply chain pressure. Vendor is 'asic-other' because 'biren' is not in the schema enum. MEMORY_BUS_WIDTH: STILL NULL, AND HERE IS PRECISELY WHAT WAS LOOKED FOR (2026-10-04). The vendor publishes NO memory-bus width for this part, and none was back-computed from the published bandwidth. NO FIGURE WAS BACK-COMPUTED FROM BANDWIDTH.[REPAIRED 2026-10-08 by w8-reverify. This sentence previously read '(2026-10-04). %s NO FIGURE WAS BACK-COMPUTED FROM BANDWIDTH' — a literal printf placeholder left in the JSON by the wave-3 pass (commit 9968769) across 34 accelerator records, and invisible to every check in this repo because validate.py never reads notes. The substitution text is the same boilerplate the 7 uncorrupted records in this family already carry, and it is only valid here because memory_bus_bit is null on every one of the 34, so "the vendor does not publish it" is the true state. A record with a non-null memory_bus_bit must NOT receive this filler.] That is the standing rule for this field in this repo and it was applied to every null here rather than to a subset: a width derived by dividing a published aggregate bandwidth by an assumed or half-assumed per-pin rate is two inferences stacked on one number, and if either inference is wrong the record looks populated while being wrong. The correct state of this field is 'the vendor does not publish it', and the note above names the specific document that was read and found not to carry it, so a future pass does not have to re-establish that from scratch. MEMORY_BUS_WIDTH: STILL NULL, AND HERE IS PRECISELY WHAT WAS LOOKED FOR (2026-10-04). Biren publishes no memory bus width for the BR100, BR104 or BILI 166 parts. The Hot Chips BR100 presentation is a floorplan-level talk and states capacity and the two-die topology, not an interface width. NO FIGURE WAS BACK-COMPUTED FROM BANDWIDTH. That is the standing rule for this field in this repo and it was applied to every null here rather than to a subset: a width derived by dividing a published aggregate bandwidth by an assumed or half-assumed per-pin rate is two inferences stacked on one number, and if either is wrong the record looks populated while being wrong. The correct state of this field is 'the vendor does not publish it', and the text above names the specific document read and found not to carry it, so a future pass does not have to re-establish that from scratch.