inference/research
verifiedhigh · 0.90updated 2026-10-03

Google Cloud TPU v5p

google v5p 2023

Fields

id
accelerators/google-tpu-v5p
Vendor
google
Architecture
v5p
Release year
2023
Process (nm)
7
Form factors
custom
VRAM (GB)
95
Memory type
hbm2e
Memory bandwidth (GB/s)
2,765
Bandwidth basis
Vendor-published per-chip HBM2e bandwidth of 2765 GBps; bus width not stated.
Peak FLOPS
precisionbf16tflops459denseyesvendor_claimyessource_idasic-tpu-v5p-specsbasisvendor-spec-sheetbasis_detailTranscribed from the vendor's own bf16 for Google Cloud TPU v5p (source of record: 'Cloud TPU v5p system architecture', kind: spec-sheet). Recorded dense:true as printed.precisionfp8tflops459denseyesvendor_claimyessource_idasic-tpu-v5p-specsbasisvendor-spec-sheetbasis_detailTranscribed from the vendor's own fp8 for Google Cloud TPU v5p (source of record: 'Cloud TPU v5p system architecture', kind: spec-sheet). Recorded dense:true as printed.
Unified memory
yes
Consumer part
no
notes
Per-chip figures. CONTESTED on FP8 semantics: the spec table states 'Peak compute per chip (FP8) (TFLOPs) 459', identical to BF16, which means the table is not counting the FP8 x2 rate-up that third-party spec sites (mirrorfrog, gpuadvisor, rooflinenotes) report as 918 FP8 TFLOPS. Either Google is quoting a dense/undoubled figure or the docs are wrong; both numbers are recorded in sources. Do not use 459 as a BF16-vs-FP8 ratio. Two TensorCores plus four SparseCores per chip, 95 GiB HBM2e, ICI 1200 GBps bidirectional per chip on a 3D torus, full pod 8960 chips (max single slice 6144 / 16x16x24). Twisted-torus variants raise theoretical bisection bandwidth ~70% at 4x4x8; Google reports only 1-2 points of MFU gain on FSDP MaxText, so the topology choice matters far less than headline numbers suggest. A BF16 intensity of 166 FLOP/byte still puts batch-1 decode in the memory-bound regime. MEMORY_BUS_WIDTH: STILL NULL, AND HERE IS PRECISELY WHAT WAS LOOKED FOR (2026-10-04). The vendor publishes no memory-bus width for this part, and none was back-computed from the published bandwidth. This is the correct state of the field for a part with no vendor width figure.

Notes

Per-chip figures. CONTESTED on FP8 semantics: the spec table states 'Peak compute per chip (FP8) (TFLOPs) 459', identical to BF16, which means the table is not counting the FP8 x2 rate-up that third-party spec sites (mirrorfrog, gpuadvisor, rooflinenotes) report as 918 FP8 TFLOPS. Either Google is quoting a dense/undoubled figure or the docs are wrong; both numbers are recorded in sources. Do not use 459 as a BF16-vs-FP8 ratio. Two TensorCores plus four SparseCores per chip, 95 GiB HBM2e, ICI 1200 GBps bidirectional per chip on a 3D torus, full pod 8960 chips (max single slice 6144 / 16x16x24). Twisted-torus variants raise theoretical bisection bandwidth ~70% at 4x4x8; Google reports only 1-2 points of MFU gain on FSDP MaxText, so the topology choice matters far less than headline numbers suggest. A BF16 intensity of 166 FLOP/byte still puts batch-1 decode in the memory-bound regime. MEMORY_BUS_WIDTH: STILL NULL, AND HERE IS PRECISELY WHAT WAS LOOKED FOR (2026-10-04). The vendor publishes no memory-bus width for this part, and none was back-computed from the published bandwidth. This is the correct state of the field for a part with no vendor width figure.

Cross-references

Interconnect (1)