inference/research
verifiedhigh · 0.85updated 2026-10-11

Hailo-15H

asic-other Hailo Vision Processor SoC 2023

Fields

id
accelerators/hailo-15h
Vendor
asic-other
Architecture
Hailo Vision Processor SoC
Release year
2023
Form factors
socs
Memory type
lpddr4
Peak FLOPS
precisionint8tflops20denseyesvendor_claimyessource_idhailo-15h-product-pagebasisvendor-spec-sheetbasis_detailHailo-15H product page states '20 TOPS (Tera Operations Per Second) running on a powerful' neural core for vision AI.unit—
TDP (W)
5
Unified memory
no
Consumer part
no
notes
REAL VENDOR: Hailo (Tel Aviv, Israel). Set to 'asic-other' because the schema enum does not include 'hailo'. Hailo-15H is an AI vision processor SoC designed for mid-to-high-end smart IP cameras, combining image signal processing (AI-powered ISP) with a 20 TOPS INT8 deep learning neural core. Typical power consumption is rated at sub-5W (<5W). The SoC requires external DRAM with a published minimum requirement of 2GB LPDDR4. Software runtime support is provided by HailoRT and the Hailo Vision Processor Software Package, deploying models exported from ONNX and LiteRT (TFLite). MEMORY FIGURES AND BANDWIDTH: STILL NULL, AND HERE IS PRECISELY WHAT WAS LOOKED FOR (2026-10-11). Hailo specifies a minimal DRAM requirement of 2GB LPDDR4 for camera systems utilizing the SoC, but the SoC itself contains no integrated VRAM package. Memory bus width and bandwidth depend on board implementation and are not published as a fixed silicon parameter. No numbers were assumed or back-computed.

Notes

REAL VENDOR: Hailo (Tel Aviv, Israel). Set to 'asic-other' because the schema enum does not include 'hailo'. Hailo-15H is an AI vision processor SoC designed for mid-to-high-end smart IP cameras, combining image signal processing (AI-powered ISP) with a 20 TOPS INT8 deep learning neural core. Typical power consumption is rated at sub-5W (<5W). The SoC requires external DRAM with a published minimum requirement of 2GB LPDDR4. Software runtime support is provided by HailoRT and the Hailo Vision Processor Software Package, deploying models exported from ONNX and LiteRT (TFLite). MEMORY FIGURES AND BANDWIDTH: STILL NULL, AND HERE IS PRECISELY WHAT WAS LOOKED FOR (2026-10-11). Hailo specifies a minimal DRAM requirement of 2GB LPDDR4 for camera systems utilizing the SoC, but the SoC itself contains no integrated VRAM package. Memory bus width and bandwidth depend on board implementation and are not published as a fixed silicon parameter. No numbers were assumed or back-computed.

Cross-references

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