inference/research
draftlow · 0.50updated 2026-10-03

Horizon Robotics Journey 6P (Nash BPU automotive SoC)

asic-other BPU 3.0 Nash 2024
This record is a draft. Not yet verified. Provisional. Treat every number on this page as provisional.

Fields

id
accelerators/horizon-journey-6p
Vendor
asic-other
Architecture
BPU 3.0 Nash
Release year
2024
Process (nm)
7
Form factors
socs
Memory type
lpddr5x
Memory bandwidth (GB/s)
204
Bandwidth basis
Secondary source citing Horizon's own launch material: 'uses LPDDR5x-8533 RAM for a total of 204 GB/s of bandwidth'. LPDDR5x-8533 is a pin rate, so the implied bus width is derivable: 204e9 / (8533e6/8) = 191 bits, i.e. a 192-bit bus. The 204 GB/s figure is therefore arithmetically self-consistent with the stated memory type and speed, which is a useful internal consistency check on the number, though it remains a secondary-source figure. Source cn-horizon-journey6.
Peak FLOPS
precisionint8tflops560denseyesvendor_claimnosource_idcn-horizon-journey6basissecondary-aggregatorbasis_detailJourney 6P '560 TOPS' from Wikipedia citing Horizon's launch material. The aggregator does not state the precision of the 560, so this row is an UNATTRIBUTED PRECISION, not a second path: it duplicates the int8 row rather than adding a figure.precisionfp64tflops560denseyesvendor_claimnosource_idcn-horizon-journey6basissecondary-aggregatorbasis_detailJourney 6P '560 TOPS' from Wikipedia citing Horizon's launch material. The aggregator does not state the precision of the 560, so this row is an UNATTRIBUTED PRECISION, not a second path: it duplicates the int8 row rather than adding a figure.
Unified memory
no
Consumer part
no
notes
THE HIERARCHY POINT: RECORDED WITH AN EXPLICIT NEGATIVE FINDING, which is the point of including it at all: Horizon Robotics (地平线, HKEX 9660) is NOT a plausible source of LLM inference hardware, and the reasoning is quantitative rather than rhetorical. Journey 6P tops out its entire range at 560 TOPS INT8 from 4 Nash BPU cores (vendor claim, secondary-sourced), and that number is not comparable to the datacenter parts in this repo because it is INT8-only automotive inference throughput for a fixed perception workload, on 7 nm TSMC, with LPDDR5x at 204 GB/s and no HBM anywhere. Put plainly: 204 GB/s of LPDDR5x is the SAME memory bandwidth as a Huawei Ascend 310P inference card, and the 310P is a 2022 part. A device with this memory subsystem cannot serve a model whose weights exceed a few gigabytes at any useful batch size, because weights have to stream from LPDDR on every decode step. The whole product is designed around a bounded, mostly-static workload - perception, planning, and increasingly a small onboard transformer - which Horizon explicitly claims to optimise for ('designed to handle high-parameter transformer models, and is optimized to run end-to-end architectures'). THE DETAIL THAT MAKES IT WORTH RECORDING ANYWAY: Journey 6 is the first Horizon generation built for Transformers rather than CNNs - Journey 5 (128 TOPS BPU Bayesian, TSMC 16 nm) was the first transformer-optimised part and Journey 6 moves to out-of-order Cortex-A78AE CPU cores and Mali G78AE 3D graphics, integrating CPU, BPU, GPU and MCU into one SoC. So the architectural direction is toward transformers. But direction is not capacity. Horizon's own market position confirms the mismatch: it shipped on navigate-on-autopilot vehicles in China at a reported 49% share of the Chinese self-driving chip market in 2023, targeting over 10 million chips in 2025, with a Volkswagen JV (Carizon) and programs with SAIC, BYD, Li Auto, GAC, Chery and Bosch, Denso and Continental as interested Tier-1s. None of that is datacenter compute. THE ONE PART THAT IS ACTUALLY IN SCOPE IS THE ROADMAP, NOT THE SILICON: Horizon announced the Journey 7 family in March 2026 on a fourth-generation BPU called Riemann, arriving 2027, whose top part J7P is claimed to significantly surpass the 1000-TOPS Nvidia Thor-X and compete with Tesla's rumoured AI5 at 2000-2500 TOPS. Those are automotive TOPS figures and still would not make this an LLM serving part - a 2500 TOPS automotive NPU with LPDDR and a fixed small memory is still not a text-generation accelerator. If a domestic vendor ever ships a general-purpose Horizon part with HBM, that would be a new record; Journey 6P is not it. Design for context: 37 billion transistors, 18-core CPU at 410k DMIPS, ISP with 24 channels handling 4K video, 18MP cameras, mmWave radar and LiDAR, mass production expected Q3 2025.

Notes

THE HIERARCHY POINT: RECORDED WITH AN EXPLICIT NEGATIVE FINDING, which is the point of including it at all: Horizon Robotics (地平线, HKEX 9660) is NOT a plausible source of LLM inference hardware, and the reasoning is quantitative rather than rhetorical. Journey 6P tops out its entire range at 560 TOPS INT8 from 4 Nash BPU cores (vendor claim, secondary-sourced), and that number is not comparable to the datacenter parts in this repo because it is INT8-only automotive inference throughput for a fixed perception workload, on 7 nm TSMC, with LPDDR5x at 204 GB/s and no HBM anywhere. Put plainly: 204 GB/s of LPDDR5x is the SAME memory bandwidth as a Huawei Ascend 310P inference card, and the 310P is a 2022 part. A device with this memory subsystem cannot serve a model whose weights exceed a few gigabytes at any useful batch size, because weights have to stream from LPDDR on every decode step. The whole product is designed around a bounded, mostly-static workload - perception, planning, and increasingly a small onboard transformer - which Horizon explicitly claims to optimise for ('designed to handle high-parameter transformer models, and is optimized to run end-to-end architectures'). THE DETAIL THAT MAKES IT WORTH RECORDING ANYWAY: Journey 6 is the first Horizon generation built for Transformers rather than CNNs - Journey 5 (128 TOPS BPU Bayesian, TSMC 16 nm) was the first transformer-optimised part and Journey 6 moves to out-of-order Cortex-A78AE CPU cores and Mali G78AE 3D graphics, integrating CPU, BPU, GPU and MCU into one SoC. So the architectural direction is toward transformers. But direction is not capacity. Horizon's own market position confirms the mismatch: it shipped on navigate-on-autopilot vehicles in China at a reported 49% share of the Chinese self-driving chip market in 2023, targeting over 10 million chips in 2025, with a Volkswagen JV (Carizon) and programs with SAIC, BYD, Li Auto, GAC, Chery and Bosch, Denso and Continental as interested Tier-1s. None of that is datacenter compute. THE ONE PART THAT IS ACTUALLY IN SCOPE IS THE ROADMAP, NOT THE SILICON: Horizon announced the Journey 7 family in March 2026 on a fourth-generation BPU called Riemann, arriving 2027, whose top part J7P is claimed to significantly surpass the 1000-TOPS Nvidia Thor-X and compete with Tesla's rumoured AI5 at 2000-2500 TOPS. Those are automotive TOPS figures and still would not make this an LLM serving part - a 2500 TOPS automotive NPU with LPDDR and a fixed small memory is still not a text-generation accelerator. If a domestic vendor ever ships a general-purpose Horizon part with HBM, that would be a new record; Journey 6P is not it. Design for context: 37 billion transistors, 18-core CPU at 410k DMIPS, ISP with 24 channels handling 4K video, 18MP cameras, mmWave radar and LiDAR, mass production expected Q3 2025.

Cross-references

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