id
accelerators/huawei-ascend-950dt
Architecture
da-vinci (950-series)
Memory type
on-chip memory (Huawei-developed; not HBM)
Memory bandwidth (GB/s)
500
Bandwidth basis
PER NPU, DERIVED BY DIVISION from the server figure: the Atlas 650E specification gives '8 x 96 GB total, 4.0 TB/s peak memory bandwidth', so each 950DT carries 96 GB at 4.0/8 = 500 GB/s. Huawei states the 4.0 TB/s server figure directly and does not publish a per-NPU breakdown; the division is arithmetic, not a claim. Note this is ON-CHIP memory, not HBM - Huawei describes it as 'Huawei's self-developed on-chip memory', which is a materially different memory technology from the HBM2e on the 910 generation and should not be compared to HBM3 bandwidth numbers without reading the vendor's wording. Source cn-huawei-atlas-650e-spec.
Peak FLOPS
precisionfp16tflops425denseyesvendor_claimyessource_idcn-huawei-atlas-650e-specbasisderivedbasis_detailDERIVED, not transcribed: Huawei publishes the Atlas 650E cabinet total; this value is that total divided by 8 NPUs. basis was 'vendor-spec-sheet' until 2026-10-05, which misrepresented a derivation as a quotation.precisionbf16tflops425denseyesvendor_claimyessource_idcn-huawei-atlas-650e-specbasisderivedbasis_detailDERIVED, not transcribed: Huawei publishes the Atlas 650E cabinet total; this value is that total divided by 8 NPUs. basis was 'vendor-spec-sheet' until 2026-10-05, which misrepresented a derivation as a quotation.precisionfp8tflops803.75denseyesvendor_claimyessource_idcn-huawei-atlas-650e-specbasisderivedbasis_detailDERIVED, not transcribed: Huawei publishes the Atlas 650E cabinet total; this value is that total divided by 8 NPUs. basis was 'vendor-spec-sheet' until 2026-10-05, which misrepresented a derivation as a quotation.precisionfp4_block_scaledtflops1,560denseyesvendor_claimyessource_idcn-huawei-atlas-650e-specbasisderivedbasis_detailPER-NPU value, DERIVED not published: Atlas 650E server figure 12.48 PFLOPS mxFP4 / 8 NPUs = 1.56 PFLOPS = 1560 TFLOPS per 950DT. Huawei publishes server figures only, so no per-NPU table exists. Vendor-theoretical, per Huawei's own 'theoretical computing power may have a <1% error' disclaimer. DUPLICATE ROW REMOVED 2026-10-04 (w3f basis backfill): this record previously carried TWO byte-identical 1560 TFLOPS rows, one filed as precision 'other' and one as 'fp4_block_scaled'. Same number, same source, same derivation (12.48 PFLOPS / 8), so the 'other' row was a second label on one quantity rather than a second hardware path. One row retained. The removed row was NOT an FP64 figure - this record has no FP64 row and none was invented.notesDUPLICATE ROW REMOVED 2026-10-04: see basis_detail. The prior precision:'other' row at 1560 TFLOPS was the same mxFP4 quantity as this fp4_block_scaled row, not an FP64 figure and not a distinct path.
notes
HUAWEI'S OWN TWO PAGES DISAGREE BY 14.3% PER NPU. Recorded 2026-10-05, previously the record presented Atlas 650E and Atlas 950 SuperPoD as if they agreed. They do not:
Atlas 650E (8 NPU) -> 1,560 / 803.75 / 425 TFLOPS per NPU (mxFP4 / FP8 / FP16)
Atlas 950 SuperPoD (64 NPU) -> 1,783 / 918.75 / 486 TFLOPS per NPU
The SuperPoD figures are 1.143x the 650E figures across all three precisions, consistently - which points at a different clock or a different NPU SKU under the SuperPoD rather than an arithmetic slip. This record stores the 650E-derived set. Both are kept here rather than one being deleted, because the repo cannot currently say which configuration a buyer receives.
SECOND DEFECT, same pass: the fp16 / bf16 / fp8 rows are marked basis 'vendor-spec-sheet' but are per-NPU DERIVATIONS (Huawei publishes cabinet totals; dividing by 8 is ours). Only fp4_block_scaled was marked 'derived'. That inconsistency let three derived figures pass as transcribed ones - the exact defect the required basis field was added to prevent. All three are now marked 'derived'.