NVIDIA GeForce RTX 5070 Ti
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accelerators/nvidia-rtx-5070-tiNotes
AUDIT 2026-10-03 (NVIDIA dense/sparse convention re-verified from the primary whitepaper PDF, no values changed): NVIDIA's GeForce RTX Blackwell architecture whitepaper (source consumer-nvidia-rtx-blackwell-gpu-architecture-whitepaper, images.nvidia.com/aem-dam/Solutions/geforce/blackwell/) prints every tensor row in the form 'DENSE/SPARSE' and defines the second number in a single footnote that is identical on every appendix page: 'Effective TOPS / TFLOPS using the Sparsity Feature'. Every 'Peak ... Tensor TFLOPS' and 'Peak INT8 Tensor TOPS' row on the sheet therefore carries that marker, while the 'non-Tensor' rows (FP32/FP16/BF16 non-tensor, Peak INT32 TOPS non-Tensor) and the RT TFLOPS row do NOT. Each sparse row was re-checked against that sheet page by page and every dense:false row on this record corresponds to a printed second number, with its dense twin present as a separate dense:true row. Note the sheet's own footnote 1, 'Peak rates are based on GPU Boost Clock' - these are boost-clock peaks, not sustained, and not measured. GB203 appendix, Table 5 'GeForce RTX 5070 Ti vs GeForce RTX 4070 Ti vs GeForce RTX 3070 Ti Specs' (PDF page 52): 'Peak FP4 Tensor TFLOPS with FP32 Accumulate (FP4 AI TOPS) 703/1406'. So fp4 1406 stored here as dense:false is the sparse column and its dense twin 703 is stored separately - correct. Note this is a GB203 part with 8960 CUDA cores vs the RTX 5080's 10,752, and NVIDIA prints both cards off the same appendix because they share the die; the 5080's higher numbers come from its higher boost clock (2617 MHz vs 2452 MHz) and full-die enablement, not from more silicon. Entry-level Blackwell consumer part, 8960 CUDA cores, 2452 MHz boost, 300 W TGP, PCIe Gen5, 49152 KB L2. Included briefly as the low-VRAM end of the 50 series.
PRECISION CAVEAT - the single most conflated number on consumer hardware. NVIDIA's product pages advertise 'AI TOPS' (5090: 3352, 5080: 1801, 5070 Ti: 1406). The RTX Blackwell whitepaper labels the identical figure 'Peak FP4 Tensor TFLOPS with FP32 Accumulate (FP4 AI TOPS) 1676/3352', where the second value uses the 2:4 structured-sparsity feature (footnote 2: 'Effective TOPS / TFLOPS using the Sparsity Feature'). So the marketing 'AI TOPS' number is FP4 with 2:4 sparsity, not INT4, not FP16, and not dense. It is not comparable to an FP16/BF16 dense figure, to the INT4-vs-FP16 speedup ratios quoted in quantization literature, or to another vendor's dense INT8 number. Only figures NVIDIA publishes with an explicit dense/sparse split are recorded here; every flops entry's dense flag states which half it is.
Inference: 16 GB at 896 GB/s. Bandwidth is respectable; capacity is the binding constraint. At 16 GB a 13B-class model in 4-bit leaves very little room for KV cache at long context, whereas a 24 GB card (4090, 5080-class) fits the same model with headroom. Capacity and bandwidth are separate axes and must be read together. INTERCONNECT FILLED 2026-10-04: interconnect was empty; it now reads ['pcie-gen5'], from the vendor's own spec table (source the GeForce RTX 5070 family product page's 'Technology Support' row). SCALE-UP IS ABSENT AND THAT IS THE POINT: this part has no NVLink and no other GPU-to-GPU fabric, so the host link is the ONLY interconnect a multi-GPU deployment has. Do not infer a fabric from the presence of a PCIe value, and do not read the Gen number as a multi-GPU capability.