verifiedhigh · 0.95updated 2026-10-05

NVIDIA GeForce RTX 5090

nvidia blackwell (GB202) 2025

Fields

accelerators/nvidia-rtx-5090

Vendor

nvidia

Architecture

blackwell (GB202)

Release year

2025

Process (nm)

Form factors

VRAM (GB)

Memory type

gddr7

Memory bus (bit)

512

Memory bandwidth (GB/s)

1,792

Bandwidth basis

GDDR7 28 Gbps data rate x 512-bit / 8 = 1792 GB/s (NVIDIA RTX Blackwell whitepaper: 'Memory Clock (Data Rate) 28 Gbps', 'Memory Bandwidth 1792 GB/sec', and in prose 'The GeForce RTX 5090 ships with 28 Gbps GDDR7 memory and delivers 1.792 TB/sec peak memory bandwidth')

On-chip cache

[object Object]

Peak FLOPS

precisionfp32tflops104.8denseyesvendor_claimyessource_idconsumer-nvidia-rtx-blackwell-gpu-architecture-whitepaperbasisvendor-whitepaperbasis_detailTranscribed from the vendor's own fp32 for NVIDIA GeForce RTX 5090 (source of record: 'NVIDIA RTX Blackwell GPU Architecture whitepaper (GeForce RTX 50 series)', kind: whitepaper). Recorded dense:true as printed.precisionfp16tflops209.5denseyesvendor_claimyessource_idconsumer-nvidia-rtx-blackwell-gpu-architecture-whitepaperbasisvendor-whitepaperbasis_detailTranscribed from the vendor's own fp16 for NVIDIA GeForce RTX 5090 (source of record: 'NVIDIA RTX Blackwell GPU Architecture whitepaper (GeForce RTX 50 series)', kind: whitepaper). Recorded dense:true as printed.precisionbf16tflops209.5denseyesvendor_claimyessource_idconsumer-nvidia-rtx-blackwell-gpu-architecture-whitepaperbasisvendor-whitepaperbasis_detailTranscribed from the vendor's own bf16 for NVIDIA GeForce RTX 5090 (source of record: 'NVIDIA RTX Blackwell GPU Architecture whitepaper (GeForce RTX 50 series)', kind: whitepaper). Recorded dense:true as printed.precisiontf32tflops104.8denseyesvendor_claimyessource_idconsumer-nvidia-rtx-blackwell-gpu-architecture-whitepaperbasisvendor-whitepaperbasis_detailTranscribed from the vendor's own tf32 for NVIDIA GeForce RTX 5090 (source of record: 'NVIDIA RTX Blackwell GPU Architecture whitepaper (GeForce RTX 50 series)', kind: whitepaper). Recorded dense:true as printed.precisionfp8tflops419denseyesvendor_claimyessource_idconsumer-nvidia-rtx-blackwell-gpu-architecture-whitepaperbasisvendor-whitepaperbasis_detailTranscribed from the vendor's own fp8 for NVIDIA GeForce RTX 5090 (source of record: 'NVIDIA RTX Blackwell GPU Architecture whitepaper (GeForce RTX 50 series)', kind: whitepaper). Recorded dense:true as printed.precisionfp8tflops838densenovendor_claimyessource_idconsumer-nvidia-rtx-blackwell-gpu-architecture-whitepaperbasisvendor-whitepaperbasis_detailTranscribed from the vendor's own fp8 for NVIDIA GeForce RTX 5090 (source of record: 'NVIDIA RTX Blackwell GPU Architecture whitepaper (GeForce RTX 50 series)', kind: whitepaper). Recorded dense:false - the vendor prints this as a structured-sparsity figure; the dense companion row on this record is the halved value. See this record's notes for the sparsity-footnote rule.precisionfp4tflops1,676denseyesvendor_claimyessource_idconsumer-nvidia-rtx-blackwell-gpu-architecture-whitepaperbasisvendor-whitepaperbasis_detailTranscribed from the vendor's own fp4 for NVIDIA GeForce RTX 5090 (source of record: 'NVIDIA RTX Blackwell GPU Architecture whitepaper (GeForce RTX 50 series)', kind: whitepaper). Recorded dense:true as printed.precisionfp4tflops3,352densenovendor_claimyessource_idconsumer-nvidia-rtx-blackwell-gpu-architecture-whitepaperbasisvendor-whitepaperbasis_detailTranscribed from the vendor's own fp4 for NVIDIA GeForce RTX 5090 (source of record: 'NVIDIA RTX Blackwell GPU Architecture whitepaper (GeForce RTX 50 series)', kind: whitepaper). Recorded dense:false - the vendor prints this as a structured-sparsity figure; the dense companion row on this record is the halved value. See this record's notes for the sparsity-footnote rule.precisionint8tflops838denseyesvendor_claimyessource_idconsumer-nvidia-rtx-blackwell-gpu-architecture-whitepaperbasisvendor-whitepaperbasis_detailTranscribed from the vendor's own int8 for NVIDIA GeForce RTX 5090 (source of record: 'NVIDIA RTX Blackwell GPU Architecture whitepaper (GeForce RTX 50 series)', kind: whitepaper). Recorded dense:true as printed.

TDP (W)

575

Unified memory

Consumer part

yes

notes

AUDIT 2026-10-03 (NVIDIA dense/sparse convention re-verified from the primary whitepaper PDF, no values changed): NVIDIA's GeForce RTX Blackwell architecture whitepaper (source consumer-nvidia-rtx-blackwell-gpu-architecture-whitepaper, images.nvidia.com/aem-dam/Solutions/geforce/blackwell/) prints every tensor row in the form 'DENSE/SPARSE' and defines the second number in a single footnote that is identical on every appendix page: 'Effective TOPS / TFLOPS using the Sparsity Feature'. Every 'Peak ... Tensor TFLOPS' and 'Peak INT8 Tensor TOPS' row on the sheet therefore carries that marker, while the 'non-Tensor' rows (FP32/FP16/BF16 non-tensor, Peak INT32 TOPS non-Tensor) and the RT TFLOPS row do NOT. Each sparse row was re-checked against that sheet page by page and every dense:false row on this record corresponds to a printed second number, with its dense twin present as a separate dense:true row. Note the sheet's own footnote 1, 'Peak rates are based on GPU Boost Clock' - these are boost-clock peaks, not sustained, and not measured. GB202 appendix (page 49 of the PDF): 'Peak FP4 Tensor TFLOPS with FP32 Accumulate (FP4 AI TOPS) 1676/3352', 'Peak FP8 Tensor TFLOPS with FP16 Accumulate 419/838', 'Peak FP8 Tensor TFLOPS with FP32 Accumulate 209.5/419', 'Peak FP16 Tensor TFLOPS with FP16 Accumulate 419/838', 'Peak FP16 Tensor TFLOPS with FP32 Accumulate 209.5/419', 'Peak BF16 Tensor TFLOPS with FP32 Accumulate 209.5/419', 'Peak TF32 Tensor TFLOPS 104.8/209.6', 'Peak INT8 Tensor TOPS 838/1676'. So fp8 838 and fp4 3352 stored here with dense:false are the SPARSE column, and their dense twins (419 and 1676) are present as separate dense:true rows - the convention is applied correctly. 21760 CUDA cores, 2.41 GHz boost / 2.01 GHz base, 575 W TGP, PCIe Gen5, 98304 KB L2, 32 GB GDDR7 on a 512-bit bus. PRECISION CAVEAT - the single most conflated number on consumer hardware. NVIDIA's product pages advertise 'AI TOPS' (5090: 3352, 5080: 1801, 5070 Ti: 1406). The RTX Blackwell whitepaper labels the identical figure 'Peak FP4 Tensor TFLOPS with FP32 Accumulate (FP4 AI TOPS) 1676/3352', where the second value uses the 2:4 structured-sparsity feature (footnote 2: 'Effective TOPS / TFLOPS using the Sparsity Feature'). So the marketing 'AI TOPS' number is FP4 with 2:4 sparsity, not INT4, not FP16, and not dense. It is not comparable to an FP16/BF16 dense figure, to the INT4-vs-FP16 speedup ratios quoted in quantization literature, or to another vendor's dense INT8 number. Only figures NVIDIA publishes with an explicit dense/sparse split are recorded here; every flops entry's dense flag states which half it is. Notable datapath ratios worth keeping straight (all DENSE): FP4 1676 = 2x INT8 838 = 4x BF16 209.5. So on this part the low-precision tensor paths are where Blackwell's consumer throughput growth lives; the BF16 path is comparatively small. Any claim that a 5090 'does 3352 TOPS of FP16' is wrong by 8x. GeForce Blackwell dropped NVLink: there is no NVLink connector on the 5090, so multi-GPU runs over PCIe only. The 32 GB at 1792 GB/s combination is the strongest consumer memory subsystem here, and it is what lets a 30B-class model run in bf16/fp8 on a single card. ACCUMULATE-MODE DISAMBIGUATION (why there is only one fp16/fp8 entry each): NVIDIA's whitepapers print separate tensor rows per accumulate mode, and the same numeric value can appear as DENSE in one row and SPARSE in another. E.g. on the 4090 'Peak FP16 Tensor TFLOPS with FP16 Accumulate 330.3/660.6' and 'Peak FP16 Tensor TFLOPS with FP32 Accumulate 165.2/330.4' - so 330.3 is DENSE-with-FP16-accumulate and SPARSE-with-FP32-accumulate. Encoding that as a single dense:false entry would be wrong. The flops array here therefore records ONE entry per precision, always the FP32-accumulate figure, because that is what LLM inference kernels use; the FP16-accumulate variants are stated in this note instead of being mislabeled as sparse. 5090 FP16-accumulate variants: fp16 dense 419 / sparse 838 TFLOPS; bf16 dense 419 / sparse 838 TFLOPS; fp8 (fp16 accumulate) dense 838 / sparse 1676 TFLOPS. The recorded fp16 209.5 / bf16 209.5 / fp8 419 entries are all FP32-accumulate dense. INTERCONNECT FILLED 2026-10-04: interconnect was empty; it now reads ['pcie-gen5'], from the vendor's own spec table (source the GeForce RTX 5090 product page's 'Technology Support' row). SCALE-UP IS ABSENT AND THAT IS THE POINT: this part has no NVLink and no other GPU-to-GPU fabric, so the host link is the ONLY interconnect a multi-GPU deployment has. Do not infer a fabric from the presence of a PCIe value, and do not read the Gen number as a multi-GPU capability. ON-CHIP CACHE ROW ADDED 2026-10-05 (schema authority pass, agent w5-schema). 98304 KB L2 was already stated in these notes and was unqueryable; schemas/accelerator.schema.json now carries onchip_cache so it can be filtered instead of grepped. Verified against the first-party whitepaper named in source_note. This figure matters for inference specifically because a 96 MB L2 is large enough that a whole layer of weights can be served from cache rather than GDDR7, which is the 'large-L2 parts' workaround flop record decode-gemm names - the note that a layer's weights can be served from cache rather than HBM is the one hardware condition under which that workaround pays off. No new number was introduced.

Notes

PRECISION CAVEAT - the single most conflated number on consumer hardware. NVIDIA's product pages advertise 'AI TOPS' (5090: 3352, 5080: 1801, 5070 Ti: 1406). The RTX Blackwell whitepaper labels the identical figure 'Peak FP4 Tensor TFLOPS with FP32 Accumulate (FP4 AI TOPS) 1676/3352', where the second value uses the 2:4 structured-sparsity feature (footnote 2: 'Effective TOPS / TFLOPS using the Sparsity Feature'). So the marketing 'AI TOPS' number is FP4 with 2:4 sparsity, not INT4, not FP16, and not dense. It is not comparable to an FP16/BF16 dense figure, to the INT4-vs-FP16 speedup ratios quoted in quantization literature, or to another vendor's dense INT8 number. Only figures NVIDIA publishes with an explicit dense/sparse split are recorded here; every flops entry's dense flag states which half it is.

Notable datapath ratios worth keeping straight (all DENSE): FP4 1676 = 2x INT8 838 = 4x BF16 209.5. So on this part the low-precision tensor paths are where Blackwell's consumer throughput growth lives; the BF16 path is comparatively small. Any claim that a 5090 'does 3352 TOPS of FP16' is wrong by 8x.

GeForce Blackwell dropped NVLink: there is no NVLink connector on the 5090, so multi-GPU runs over PCIe only. The 32 GB at 1792 GB/s combination is the strongest consumer memory subsystem here, and it is what lets a 30B-class model run in bf16/fp8 on a single card.

ACCUMULATE-MODE DISAMBIGUATION (why there is only one fp16/fp8 entry each): NVIDIA's whitepapers print separate tensor rows per accumulate mode, and the same numeric value can appear as DENSE in one row and SPARSE in another. E.g. on the 4090 'Peak FP16 Tensor TFLOPS with FP16 Accumulate 330.3/660.6' and 'Peak FP16 Tensor TFLOPS with FP32 Accumulate 165.2/330.4' - so 330.3 is DENSE-with-FP16-accumulate and SPARSE-with-FP32-accumulate. Encoding that as a single dense:false entry would be wrong. The flops array here therefore records ONE entry per precision, always the FP32-accumulate figure, because that is what LLM inference kernels use; the FP16-accumulate variants are stated in this note instead of being mislabeled as sparse. 5090 FP16-accumulate variants: fp16 dense 419 / sparse 838 TFLOPS; bf16 dense 419 / sparse 838 TFLOPS; fp8 (fp16 accumulate) dense 838 / sparse 1676 TFLOPS. The recorded fp16 209.5 / bf16 209.5 / fp8 419 entries are all FP32-accumulate dense. INTERCONNECT FILLED 2026-10-04: interconnect was empty; it now reads ['pcie-gen5'], from the vendor's own spec table (source the GeForce RTX 5090 product page's 'Technology Support' row). SCALE-UP IS ABSENT AND THAT IS THE POINT: this part has no NVLink and no other GPU-to-GPU fabric, so the host link is the ONLY interconnect a multi-GPU deployment has. Do not infer a fabric from the presence of a PCIe value, and do not read the Gen number as a multi-GPU capability.

ON-CHIP CACHE ROW ADDED 2026-10-05 (schema authority pass, agent w5-schema). 98304 KB L2 was already stated in these notes and was unqueryable; schemas/accelerator.schema.json now carries onchip_cache so it can be filtered instead of grepped. Verified against the first-party whitepaper named in source_note. This figure matters for inference specifically because a 96 MB L2 is large enough that a whole layer of weights can be served from cache rather than GDDR7, which is the 'large-L2 parts' workaround flop record decode-gemm names - the note that a layer's weights can be served from cache rather than HBM is the one hardware condition under which that workaround pays off. No new number was introduced.

Cross-references

Interconnect (1)

InterconnectPCI Express 5.0