Coral Dev Board Edge TPU: MobileNet v2 224x224, 2.6ms -> 384.6 inf/s
384.6 inferences/s (from 2.6 ms per inference, vendor C++ benchmark)
Fields
id
benchmarks/coral-edgetpu-devboard-mobilenetv2-inf-sMetric
tps_aggregate
Value
384.6
Unit
inferences/s (from 2.6 ms per inference, vendor C++ benchmark)
Model
MobileNet v2 224x224 TFLite INT8
Methodology
VENDOR-MEASURED (Google Coral official Edge TPU benchmarks page). TFLite C++ benchmark, inference-time only (no pre/post processing). Two configs published: (a) USB Accelerator on Xeon Gold 6154 host over USB 3.0, (b) Coral Dev Board (Cortex-A53 quad @1.5GHz). Values below are the USB-Accelerator column converted ms -> inferences/sec (1000/ms). INT8 vision CNNs only - Edge TPU cannot run transformer decode; these records close the coverage gap, not an LLM claim.
Measured by
vendor
Reproducible
yes
notes
Dev Board (A53 host) column - same model as USB row; identical model-side latency. Vision-CNN rows only; the accelerator record already documents that Coral has no LLM path.
Notes
Dev Board (A53 host) column - same model as USB row; identical model-side latency. Vision-CNN rows only; the accelerator record already documents that Coral has no LLM path.