Intel Gaudi 3 scale-up and scale-out fabric - 200 GbE RDMA NIC ports over 112G PAM4 SerDes; passive on-baseboard scale-up, Ethernet scale-out via the host NIC. Intel publishes no product name for it.

PER PORT, PER DIRECTION - AND THE PER-PORT RATE IS THE ONLY FIGURE HERE THAT IS NOT AN AGGREGATE. Every other Gaudi 3 networking number is a SUM OVER PORTS, and conflating the two is the trap in this record. Intel states the port rate as '200 GbE' with the SerDes underneath it as '48 x 112G PAM4' (Table 2) and '24x 200 GbE ... via 48 112G PAM4 Serdes' (Table 4); these are per-direction Ethernet port rates by convention. The whole-card sum is the separately quoted 'Networking (bidirectional) 1200 GB/s' (Table 1). So the recorded 25.0 is 200 Gb/s / 8 = ONE port, ONE direction - NOT the card's fabric. The three useful sums, all arithmetic on vendor-stated port counts with no invented divisor: PER PORT PER DIRECTION 25 GB/s (the recorded value); FULL CARD, ALL 24 PORTS, PER DIRECTION 24 x 200 Gb/s = 600 GB/s; FULL CARD, ALL 24 PORTS, BIDIRECTIONAL 1200 GB/s, WHICH IS INTEL'S OWN TABLE 1 FIGURE VERBATIM. THE 2x IS NOT A CONVENTION ERROR TO BE 'CORRECTED' - IT IS WHAT TABLE 1 SAYS, and Table 2's 48x 112G SerDes count confirms 24 ports x 2 directions. Scale-up alone is 21 of the 24 ports: 21 x 200 Gb/s = 525 GB/s per direction per card, 1.05 TB/s bidirectional. Scale-out is the other 3, and per BASEBOARD (not per card) 8 cards x 3 x 200 GbE = 4.8 TbE, which is the '4.8 TbE' Table 4 prints. DIRECTION IS VENDOR-SUPPLIED AND ASYMMETRIC WITHIN A SINGLE TABLE, which is what makes these figures usable rather than inferred: Intel labels the networking row 'bidirectional' and the host row per-direction ('Host Interface Peak BW 128 GB/s (64 GB/s per direction)'). THE HOST LINK IS NOT ONE OF THE 24 PORTS: Table 4 lists 'x16 PCIe Gen5 host interface per OAM' separately.

SCALE-UP IS A PASSIVE BASEBOARD FABRIC AND NEEDS NO SWITCH; SCALE-OUT IS ORDINARY EXTERNAL ETHERNET. The HLB-325L baseboard holds 8 Gaudi 3 OAM cards 'passively interconnected on its PCB in a non-blocking, all-to-all configuration, using 21 NICs from each card (3x 200 GbE ports to every other of the 7 cards)' - a passive PCB fabric with no switch ASIC. Intel states the port-budget allocation verbatim: 3 of the 21 ports to each of the other 7 cards, and 'the 3 remaining 200 GbE NICs from every Intel Gaudi 3 AI accelerator card (3x8=24)' routed to six on-board OSFP800 connectors for scale-out. Table 3 names the mechanism split explicitly: 'Scale-up: Card-to-Card through Top Board / Scale-out: Through Host-NIC only' - scale-out leaves the card over Ethernet rather than over any proprietary backplane. SCALE-OUT TOPOLOGY IS PUBLISHED IN FULL (paper Fig. 15): 16 servers per sub-cluster onto 3 x 64-port 800 GbE Ethernet leaf switches, 32 sub-clusters onto 48 x 64-port 800 GbE spine switches, 512 nodes and 4096 accelerators total, which Intel describes as a '3-ply network'. Per OSFP the figure is labelled '200Gb/s Bi-Directional'. THE SCALE-UP BUDGET IS BOARD-DEPENDENT, so no single per-card number describes every Gaudi 3 system: the 8-way OAM baseboard gives 21 ports per card, but the 4-way PCIe path (HL-338 on an HLTB-304 x4 top board) gives '6x 200 GbE links from each HL-338 card to each of the other 3 HL-338 cards, 18 links of 200 GbE total per card' - 18, not 21. THE INTRA-PACKAGE LINK IS NOT THIS RECORD: the two compute dies 'are connected through a high-bandwidth, low-latency interconnect over an interposer bridge', transparent to software with NO bandwidth published, so the die-to-die figure remains genuinely open and was not inferred from anything here.

NONE FOR EITHER TIER, BY DESIGN. Gaudi 3 scale-out uses off-the-shelf Ethernet - the paper's own switches are described as '64 port 800 Gb' leaf and spine devices - so there is no Gaudi switch part and nothing proprietary to procure. Intel names board parts (HLB-325L baseboard, HLTB-304 x4 top board) but those are passive carriers, not switches. The consequence for a reader is that the Gaudi 3 fabric's scale-out tier is bought from a networking vendor, and only the scale-up tier is an Intel-specific integration problem.

ADDED 2026-10-05. Until now Gaudi's interconnect existed in this repo only as two generic tags on the accelerator records - 'ethernet-uec' and 'pcie-gen5' - which are both true and both useless for the question a reader actually has, which is how many bytes Gaudi can move between two cards. THIS RECORD IS THE ANSWER AND IT IS NON-TRIVIAL: Gaudi's scale-up tier is real, is on the baseboard, and is 21 of its 24 NIC ports, which means Intel chose to build scale-up out of the same 200 GbE ports it uses for scale-out rather than adding a proprietary low-latency fabric. That is a genuinely different architecture from NVLink, XGMI, UB or UB Link, and it is why this record exists rather than leaving Gaudi on the generic ethernet tag. WHAT MAKES THE PORT SPLIT WORTH RECORDING PRECISELY: because scale-up and scale-out are the SAME port type with a fixed per-card allocation (21 up, 3 down), the two tiers are NOT independently configurable, and 'Gaudi 3 has 1200 GB/s of networking' is true while being useless for sizing a scale-up job. The number that matters for tensor parallelism inside a node is 525 GB/s per direction per card; the 600 GB/s per direction figure is the sum of both tiers and only 3/24 of it is scale-up. A reader who sizes a fabric from the 1200 GB/s headline overestimates intra-node bandwidth by about 2.3x. THE GAUDI 2 COMPARISON, WHICH IS A FREE COROLLARY: Gaudi 2's Table 1 networking figure of '600 GB/s (bidirectional)' is exactly 12 x 200 Gb/s per direction, i.e. 24 ports at 200 Gb/s - the SAME port count and per-port rate as Gaudi 3. The generation-on-generation 2x networking gain is therefore a PORT-COUNT GAIN AT A CONSTANT PER-PORT RATE, not a faster link. That matters to anyone counting SerDes or QSFP cages on a board, and it is a correction to the natural assumption that a doubled bandwidth number means a doubled link rate. WHY THE Gaudi PCIe FIGURES WERE LEFT COMPLETELY ALONE: two prior agents established that the Gaudi PCIe numbers are correctly stored as AGGREGATE, and this record does not touch them. The host link here is referenced only to keep it distinct from the 24 NIC ports, and its published form ('128 GB/s (64 GB/s per direction)') is quoted verbatim rather than restated as a value. Anyone reconciling Gaudi's host bandwidth should read interconnect/pcie-gen5, which already carries the PCI-SIG-sourced convention analysis. CONFIDENCE 0.85 AND WHY NOT HIGHER: every number here is vendor-published and the arithmetic reconciles three ways, but the record rests on a single PDF, Intel publishes no fabric name and no latency figures, and the per-card scale-up budget genuinely varies with board (21 vs 18). The unquantified die-to-die interposer bridge inside the package is a real hole, not an oversight.