id
interconnect/marvell-cpo-6-4t
Version
Marvell 6.4T CPO Light Engine
Bandwidth (GB/s, per link, unidirectional)
800
Bandwidth basis
PER LIGHT ENGINE TILE, DIRECTION UNSTATED BY VENDOR. Marvell's technical documentation states: 'Each XPU is connected to four Marvell 6.4T light engines for opto-electric conversions. The light engines interface with two 36-fiber detachable Metallic PIC Couplers (MPCs) from SENKO.' In the CPO switch reference design: 'The ethernet switch ASIC—the large semiconductor in the center of the image—is surrounded by 16 light engine tiles and 1,152 fibers (128 laser fibers and 1,024 data fibers)', delivering 'up to 102.4 Tbps of bandwidth delivered through 1024 optical fibers'. Stated rate is 6.4 Tbps per light engine tile (= 6,400 / 8 = 800 GB/s per tile). The vendor does not explicitly qualify 6.4T as unidirectional or bidirectional aggregate in the text, so way is recorded honestly as unknown. (If 6.4T is bidirectional aggregate, per-direction throughput is 400 GB/s; if unidirectional, 800 GB/s).
Topology
Co-packaged optics (CPO) light engine tiles mounted immediately adjacent to compute XPU or Ethernet switch ASIC on a common substrate. Optical interfaces connect via detachable 36-fiber Metallic PIC Couplers (MPCs) to front-panel or blind-mate optical connectors.
Switching
Electro-optic conversion engine driven by host ASIC SerDes; external continuous-wave (CW) laser modules located at chassis faceplate driving 128 laser fibers. Reference designs demonstrated for 102.4 Tbps Ethernet switch (16 light engine tiles) and 1U 4-XPU AI scale-up compute tray (16 light engines, 1,024 data fibers).
notes
Marvell 6.4T light engine is a co-packaged optics (CPO) building block developed for both AI scale-up compute trays and scale-out Ethernet switches. Developed in collaboration with SENKO (detachable metallic PIC couplers) and Mikros Technologies (low-profile microchannel liquid cold plates).\n\nINFERENCE RELEVANCE: As multi-node LLM inference clusters expand to serve 100B+ and mixture-of-experts (MoE) models across tens to hundreds of accelerators, the electrical reach of copper PCB traces and high-speed SerDes power consumption become major bottlenecks. Co-packaging optics alongside the compute ASIC bypasses long PCB copper traces and eliminates pluggable transceiver retimers, slashing opto-electrical conversion power per bit. In scale-up server trays, 4 XPUs with four 6.4T light engines each achieve 25.6 Tbps of optical I/O per XPU across 1,024 optical fibers, expanding low-latency tensor-parallelism and expert-parallelism domains across full racks without conventional transceiver thermal and radix limits.