NVLink 1 (Pascal, Tesla P100)

PER LINK, PER DIRECTION. NOW FIRST-PARTY AND VERBATIM, upgraded 2026-10-05 from a derivation to a direct transcription. NVIDIA's Tesla P100 architecture whitepaper (w3a-nvidia-tesla-p100-whitepaper, WP-08019-001 v01.1) states both quantities explicitly and unambiguously: 'A single Link supports up to 40 GB/sec of BIDIRECTIONAL bandwidth between the endpoints. Multiple Links can be combined to form Gangs for even higher-bandwidth connectivity between processors. The NVLink implementation in Tesla P100 supports up to four Links, enabling ganged configurations with aggregate maximum bidirectional bandwidth of 160 GB/sec.' Three facts, all in one paragraph, none inferred: the PER-LINK rate is 40 GB/s BIDIRECTIONAL; the LINK COUNT is four; the PER-GPU aggregate is 160 GB/s BIDIRECTIONAL. The recorded value is therefore 40 / 2 = 20 GB/s per link per direction. DIRECTION CAUTION, and this is the whole record: NVIDIA labels the per-link figure 'bidirectional' and the per-GPU figure 'bidirectional' in the same paragraph, so 40 and 160 are BOTH aggregates across the two directions and neither may be read as a per-direction rate. Halve once to get the per-direction per-link rate; halve once more to get the per-direction per-GPU aggregate. The arithmetic is self-checking and both paths agree: 4 links x 40 = 160 as printed, and 4 x 20 x 2 = 160. The P100 datasheet (net2-nvidia-p100-datasheet) independently carries the same 160 GB/s in a chart labelled 'Bidirectional BW (GB/Sec)' against 32 GB/s for K40 and M40. PER-LINK vs PER-GPU, which is the second axis of error here and the reason this record's typed value is the small number: NVIDIA's user-facing figure for this generation is always the per-GPU 160 GB/s aggregate, so a reader who stores 'NVLink 1 = 160' and a reader who stores 'NVLink 1 = 20' are both quoting NVIDIA, for different quantities, and they differ by exactly 8x. This is the ONLY record in the nvlink-* family where NVIDIA publishes a per-link bandwidth figure at all - see the gotcha w7n-nvlink-per-link-rate-is-derived-not-published-except-gen1 for what that means for the other five generations.

Direct point-to-point links between GPU pairs. With 4 links per GPU an all-to-all mesh is impractical beyond a few GPUs: NVIDIA's own P100 material shows the 8-GPU node as 'up to eight Tesla P100 GPUs interconnected in a single node', reached by grouping the limited links per peer pair rather than by a crossbar.

None. NVSwitch did not exist at this generation - the first NVSwitch silicon shipped with DGX-2 (Volta, 2017 generation), after the Pascal P100. So an 8-P100 node is a partial mesh in which the link grouping dictates which pairs get full bandwidth and which are bandwidth-starved; there is no in-network reduction of any kind.

The first NVLink generation, added 2026-10-03 to complete the 1/2/3/4/5 ladder - the family was missing its starting point, which made the generational trend unreadable. HEADLINE CAPABILITY, the third required quantity for this generation, which the 2026-10-03 version of this record did not state at all: NVLink 1's distinguishing feature is HARDWARE-ASSISTED GPU-TO-GPU PEER-TO-PEER MEMORY ACCESS without a switch, and the mechanism NVIDIA names is GANGING - 'Multiple Links can be combined to form Gangs for even higher-bandwidth connectivity between processors' (w3a-nvidia-tesla-p100-whitepaper). Four links ganged into a wider pipe toward a single peer is the whole design, and it is why this record's 4-link count is a statement about a P2P topology rather than about four independent wires. The second headline is the memory-space unification it enabled: an eight-P100 node exposes one flat address space over eight 16 GB devices without loading stores through the host, which is the capability that distinguishes NVLink from the PCIe-only parts of the same era (see local-consumer-gpu-no-nvlink). NVIDIA's own framing of the generation's value is bandwidth-versus-alternatives rather than capability: 160 GB/s 'Bidirectional BW' against 32 GB/s for K40 and M40, advertised as '5X higher performance than current best-in-class technology'. AUDIT 2026-10-05: confidence raised 0.78 -> 0.9 and the bandwidth_basis rewritten, because the per-link bandwidth is no longer a derivation from a chart plus a Wikipedia link structure. NVIDIA's own Tesla P100 architecture whitepaper states all three quantities verbatim - 40 GB/s bidirectional PER LINK, four Links, 160 GB/s bidirectional PER-GPU aggregate - in a single paragraph that labels both bandwidth figures 'bidirectional'. Previously the record noted 'NVIDIA's public P100 materials do not publish a per-link rate'; that was wrong, and it was wrong because the datasheet was consulted and the whitepaper was not, even though the whitepaper already sat in data/sources/ cited by the P100 accelerator record. It is now cited here. Wikipedia is retained only for the sub-link differential-pair structure, which remains genuinely secondary. FIRST-PARTY CONFIRMATION OF THE 160 FIGURE FROM THE FAR END OF THE LADDER: NVIDIA's GB200 NVL72 blog (net2-nvidia-nvswitch3-blog) says 'the fifth-generation NVLink is 12x faster than the first generation at 160 GB/s, introduced in 2014' - so 160 is both the per-GPU origin figure and, per that same sentence's '12x faster', the bidirectional number NVIDIA compares against. THE GENERATIONAL TREND IS THE POINT, and it is not monotonic in per-link rate: NVLink 1 at 20 GB/s per direction per link, NVLink 2 at 25, NVLink 3 at 25 (doubling the link count 6->12 for its 2x), NVLink 4 at 25 (18 links), NVLink 5 at 50 (18 links), NVLink 6 at 41.7 (36 links). The per-link column is a DERIVED quantity for every generation except this one - NVIDIA publishes per-GPU aggregate and link count, never the per-link rate, from Gen2 onward (see gotcha w7n-nvlink-per-link-rate-is-derived-not-published-except-gen1). NVIDIA roughly tripled the per-GPU bidirectional aggregate over this span (160 -> 1,800 GB/s, 11.25x) while the per-link per-direction rate went 20 -> 25 -> 25 -> 25 -> 50, so aggregate fabric bandwidth is link_count x per-link rate, and the link count, not the SerDes, is the lever NVIDIA pulled most often. INFERENCE RELEVANCE: 80 GB/s per direction per GPU against the P100's 732 GB/s of HBM2 means the fabric was roughly 1/9th of local memory bandwidth at this generation, versus roughly 1/7th on NVLink 4's 450 against 3.35 TB/s. The ratio did not improve, which is the structural reason NVLink was not a tensor-parallel fabric when introduced: at 20 GB/s per direction per link the TP all-reduce crossover batch (docs/11-interconnect-decision.md) sits in the low hundreds, so multi-GPU P100 serving was a CAPACITY play - 8 x 16 GB - not a bandwidth play. Direct-attach also meant a partial mesh with no switch, so collective time was set by the weakest pair link.