Cerebras CS-4 / WSE-3 Turbo
spec-sheet
Fields
id
sources/asic-cerebras-cs4Publisher
Cerebras Systems
Kind
spec-sheet
Published
2026-08-18
Accessed
2026-10-03
notes
WSE-3 Turbo: 4T transistors, 900,000 cores, 250 PFLOPS, 43.2 PB/s memory bandwidth, 2 us wafer-to-wafer latency, three wafers per CS-4 system.
Notes
WSE-3 Turbo: 4T transistors, 900,000 cores, 250 PFLOPS, 43.2 PB/s memory bandwidth, 2 us wafer-to-wafer latency, three wafers per CS-4 system.
Cross-references
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