Cloud TPU v3 system architecture

Per-chip BF16 peak 123 TFLOPS, HBM2 32 GiB / 900 GBps, measured min/mean/max power 123/220/262 W, 1024-chip pod, 2D torus, 126 PFLOPS per pod, all-reduce 340 TB/s per pod, bisection 6.4 TB/s per pod. Table header reads 'v3 Pod values' even for rows that are per-chip (peak compute, HBM capacity/bandwidth, power), which is a column-label trap: the per-chip rows are per chip. NO per-chip ICI bandwidth row is published here - that figure comes from the ISCA 2017 architecture paper instead (source asic-tpu-v2-paper). Page carries no v4s/v2 spec table of its own. Last updated 2026-10-02 UTC.