inference/research
verifiedhigh · 0.85updated 2026-10-04

NVIDIA Blackwell Architecture (official product page)

spec-sheet

Fields

id
sources/bw-nv-blackwell-architecture-page
Publisher
NVIDIA
Kind
spec-sheet
Accessed
2026-10-04
notes
NVIDIA Blackwell architecture product page. Key facts: 208B transistors, TSMC 4NP process, two reticle-limited dies connected by 10 TB/s chip-to-chip interconnect (NV-HBI). Second-gen Transformer Engine with microscaling formats (FP4). Blackwell Ultra: 2x attention-layer acceleration, 1.5x more AI compute FLOPS vs Blackwell. NVLink 5 scales to 576 GPUs. NVLink Switch Chip enables 130 TB/s in 72-GPU domain, 4x bandwidth efficiency with SHARP FP8 support. GB300 NVL72: 65x more AI compute than Hopper. Decompression engine (LZ4, Snappy, Deflate). RAS engine. TEE-I/O confidential computing.

Notes

NVIDIA Blackwell architecture product page. Key facts: 208B transistors, TSMC 4NP process, two reticle-limited dies connected by 10 TB/s chip-to-chip interconnect (NV-HBI). Second-gen Transformer Engine with microscaling formats (FP4). Blackwell Ultra: 2x attention-layer acceleration, 1.5x more AI compute FLOPS vs Blackwell. NVLink 5 scales to 576 GPUs. NVLink Switch Chip enables 130 TB/s in 72-GPU domain, 4x bandwidth efficiency with SHARP FP8 support. GB300 NVL72: 65x more AI compute than Hopper. Decompression engine (LZ4, Snappy, Deflate). RAS engine. TEE-I/O confidential computing.

Cross-references

This record references no other records.