Cambricon Siyuan 370 (思元370) chip overview page

PRIMARY VENDOR SOURCE, die level. 7 nm, first Cambricon chiplet part, 39 billion transistors, max 256 TOPS INT8 at the die level (2x the Siyuan 270), MLUarch03 with a Supercharger module and multi-operator hardware fusion. First publicly released cloud AI chip to support LPDDR5. Vendor states memory bandwidth is 3x the previous generation and memory-access energy efficiency is 1.5x GDDR6's - a RELATIVE claim with no absolute number and no bus width, so it cannot be re-derived. MLU-Link gives each chip 200 GB/s of extra cross-chip direct link. Codec: 132x 1080p decode, 10x 8K decode, 42% encode bandwidth saving at equal PSNR.