Huawei CloudMatrix 384 (CM384) supernode — system architecture and specifications

PRIMARY VENDOR SOURCE (Huawei engineering paper). CloudMatrix 384 integrates 384 Ascend 910C NPUs and 192 Kunpeng CPUs interconnected via an ultra-high-bandwidth Unified Bus (UB) network. The 910C is a dual-die package: two identical compute dies co-packaged, sharing eight on-package memory stacks. System figures: ~300 PFLOPS BF16 dense, 48 TB HBM, 559 kW system power. UB uses 224 Gbps high-speed transceivers, 7 per NPU, totaling 196 GB/s unidirectional per NPU. L1 on-board switching: 7 UB Switch chips per node. L2 rack-level switching: 112 L2 UB switch chips across 4 communication racks. 6,912 800G LPO optical transceivers. Scale-out: 200 Gbps RoCE RDMA per NPU (76.8 Tbps total). DeepSeek V4 Pro inference: 6,688 tokens/s/NPU prefill, 1,943 tokens/s/NPU decode. NOTE: Huawei has since revised the paper twice — version 2 deletes the sentence giving the chip's throughput, and version 3 renames the part from Ascend 910C to Ascend 910. The figures here are from version 1. The China Research Collective analysis (June 2026) gives slightly different figures: ~289 PFLOPS BF16, 48 TB HBM, 350-500 kW.