Pinghu (平湖) 4th-generation MUSA GPU architecture page (Moore Threads)

PRIMARY VENDOR SOURCE, architecture-level. Native FP8 in the tensor compute engine (TCE) with a 24-bit FP8 accumulation mantissa vs 14-bit on the unnamed flagship; supports E4M3 and E5M2 with multiple scaling modes; hardware W4A16 and W8A16 weight dequantization; SQMMA; Tensor Memory Engine (TME) for layout and precision conversion; Asynchronous Transaction Barrier (ATB); a dedicated Asynchronous Communication Engine (ACE) that offloads data movement off the compute cores (vendor says this recovers the 15-20% of SM resources conventional in-kernel communication costs); 60 MB LLC; programmable data persistence; 2nd-generation MTLink claimed at 7x the bandwidth of gen 1 with full 8-GPU node topology. Claims FP8 GEMM efficiency >90% and FlashAttention efficiency ~95%, both vs an unnamed flagship. Still no absolute TFLOPS.