inference/research
verifiedhigh · 0.85updated 2026-10-04

TensorRT-LLM PR #18542: FMHA NVRTC JIT warmup sits on the cold-start critical path (5-11 s per kernel, 80-160 s total)

release-notes

Fields

id
sources/ev-trtllm-pr-18542-fmha-jit-warmup
Publisher
NVIDIA
Kind
release-notes
Accessed
2026-10-04
notes
Opened 2026-09-01, still OPEN as of 2026-10-04. Vendor-authored and therefore authoritative about its own cost. Exact claims from the description: at engine startup, TRTLLM-Gen FMHA generation kernels are 'NVRTC-compiled synchronously inside the first warmup forward - ~5-11s per kernel variant depending on host CPU, 80-160s total on MLA fp8-KV configs (DeepSeek-family), ~2min for sparse gen kernels. This sits directly on the engine cold-start critical path.' The proposed opt-in fix TRTLLM_GEN_FMHA_ASYNC_WARMUP=1 overlaps the compile with autotuning and graph capture; internal B200 measurement: 'warmup reduction from 163 seconds to approximately 26-30 seconds'. Note this is a DIFFERENT compile from the C++ build: runtime NVRTC codegen of kernels for the specific shapes and configs being served, paid on every cold start of a new engine.

Notes

Opened 2026-09-01, still OPEN as of 2026-10-04. Vendor-authored and therefore authoritative about its own cost. Exact claims from the description: at engine startup, TRTLLM-Gen FMHA generation kernels are 'NVRTC-compiled synchronously inside the first warmup forward - ~5-11s per kernel variant depending on host CPU, 80-160s total on MLA fp8-KV configs (DeepSeek-family), ~2min for sparse gen kernels. This sits directly on the engine cold-start critical path.' The proposed opt-in fix TRTLLM_GEN_FMHA_ASYNC_WARMUP=1 overlaps the compile with autotuning and graph capture; internal B200 measurement: 'warmup reduction from 163 seconds to approximately 26-30 seconds'. Note this is a DIFFERENT compile from the C++ build: runtime NVRTC codegen of kernels for the specific shapes and configs being served, paid on every cold start of a new engine.

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