NVIDIA CUTLASS GitHub repository

README, NOASSERTION license (NVIDIA CUTLASS Source Code License). Architecture-dependent facts used here: CUTLASS 3.0 introduced CuTe; 4.0 released the CuTe DSL (a Python kernel DSL) as the first of the CUTLASS DSLs; CUTLASS 3.x on H100 implements Tensor Core ops with mma and wgmma while the Blackwell SM100 path uses the umma/tcgen05 instructions; several Hopper and Blackwell PTX instructions are 'architecture-accelerated features' requiring an sm_90a or sm100a target. Explicit portability warning: 'The NVIDIA Blackwell SM100 architecture used in the datacenter products has a different compute capability than the one underpinning NVIDIA Blackwell GeForce RTX 50 series GPUs (SM120). As a result, kernels compiled for Blackwell SM100 architecture with arch conditional features (using sm100a) are not compatible with RTX 50 series GPUs.' Blackwell/Rubin entries list extended TMEM from 512 to 576 columns, 328KB shared-memory allocations, higher-throughput FP8 (MMA_K=64) and FP4 (MMA_K=128) Tensor Core MMA instructions, Blackwell Ultra blockscaled GEMM, and 2:4 sparsity support for FP4.