inference/research
verifiedhigh · 0.90updated 2026-10-17

sycl_ext_oneapi_matrix joint_matrix extension specification

spec-sheet

Fields

id
sources/sycl-ext-oneapi-matrix-joint-matrix-spec
Publisher
Intel
Kind
spec-sheet
Published
2024-04-29
Accessed
2026-10-17
notes
The DPC++ experimental extension that defines joint_matrix, the SYCL type that maps onto Intel XMX (and AMX, NVIDIA tensor cores, AMD matrix cores). Read on the sycl branch 2026-10-17. The document says the extension is experimental and that shipping products should not rely on it. The Intel XMX supported-combinations appendix lists the legal (M, N, K, type) tuples per architecture, including architecture::intel_gpu_pvc, and the PVC/BMG restrictions section states the stride, alignment and row_index constraints plus the IGC_JointMatrixLoadStoreOpt=1 fallback. Revision 11 (2024-04-29, Yury Plyakhin) is the one that added the 1x64x16 combination for intel_gpu_pvc; the published date recorded here is that revision, not the document's first draft (2021-04-13).

Notes

The DPC++ experimental extension that defines joint_matrix, the SYCL type that maps onto Intel XMX (and AMX, NVIDIA tensor cores, AMD matrix cores). Read on the sycl branch 2026-10-17. The document says the extension is experimental and that shipping products should not rely on it. The Intel XMX supported-combinations appendix lists the legal (M, N, K, type) tuples per architecture, including architecture::intel_gpu_pvc, and the PVC/BMG restrictions section states the stride, alignment and row_index constraints plus the IGC_JointMatrixLoadStoreOpt=1 fallback. Revision 11 (2024-04-29, Yury Plyakhin) is the one that added the 1x64x16 combination for intel_gpu_pvc; the published date recorded here is that revision, not the document's first draft (2021-04-13).

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