AMD Instinct MI300X product page specification table - dense and structured-sparse rows (VERBATIM)

VERBATIM SPEC TABLE, 'Peak <X> Performance' = DENSE, 'Peak <X> Performance with Structured Sparsity' = SPARSE: FP8 (E5M2,E4M3) 2.61 PFLOPs / 5.22 PFLOPs; FP16 1.3 PFLOPs / 2.61 PFLOPs; TF32 Matrix 653.7 TFLOPs / 1.3 PFLOPs; FP32 Matrix 163.4 TFLOPs (no sparse row) and FP32 163.4 TFLOPs; FP64 Matrix 163.4 TFLOPs and FP64 81.7 TFLOPs (no sparse row); INT8 2.6 POPs / 5.22 POPs; bfloat16 1.3 PFLOPs / 2.61 PFLOPs. Also verbatim from the same table: Peak Engine Clock 2100 MHz, Last Level Cache 256 MB, Dedicated Memory Size 192 GB, Dedicated Memory Type HBM3, Memory Interface 8192-bit, Memory Clock 5.2 GHz, Peak Memory Bandwidth 5.3 TB/s, Typical Board Power (TBP) 750W Peak, External Power Connectors 54V UBB, GPU Form Factor OAM Module, Bus Type PCIe 5.0 x16, Infinity Fabric Links 8, Peak Infinity Fabric Link Bandwidth 128 GB/s, Cooling Passive OAM, Transistor Count 153 Billion. DENSE/SPARSE FLAGS AUDITED ROW BY ROW: every dense flag in data/accelerators/amd-instinct-mi300x.json matches the basis string, and every sparse row is exactly 2x its dense partner. FP32 (163.4) is a VECTOR row with no sparse variant, so dense:true is correct by construction. NOTE the vendor prints bfloat16 with the typo 'Strutured Sparsity' - cosmetic only, and note INT8 is printed as POPs not PFLOPs, so the record's single tflops field holds an ops figure for the int8 rows. PCIe: AMD states generation and width ONLY - 'PCIe 5.0 x16' with NO bandwidth number anywhere on the page. There is therefore NO vendor-stated PCIe bandwidth for MI300X and the record stores none; it stores only the pcie-gen5 tag. The 128 GB/s in the record's notes is Infinity Fabric LINK bandwidth, a different link (on-package, 8 links) and must not be read as a host-interface figure.