AMD Instinct MI325X product page specification table - dense and structured-sparse rows (VERBATIM)

VERBATIM SPEC TABLE: FP8 2.61 PFLOPs / 5.22 PFLOPs with Structured Sparsity; FP16 1.3 / 2.61 PFLOPs; TF32 Matrix 653.7 TFLOPs / 1.3 PFLOPs; FP32 Matrix 163.4 TFLOPs; FP64 Matrix 163.4 TFLOPs and FP64 81.7 TFLOPs; INT8 2.6 POPs / 5.22 POPs; bfloat16 1.3 PFLOPs / 2.61 PFLOPs. Peak Engine Clock 2100 MHz, LLC 256 MB, Dedicated Memory Size 256 GB, Dedicated Memory Type HBM3E, Memory Interface 8192-bit, Memory Clock 6 GHz, Peak Memory Bandwidth 6 TB/s, Memory ECC Support Yes (Full-Chip), TBP 1000W Peak, 54V UBB, OAM Module, Bus Type PCIe 5.0 x16, Infinity Fabric Links 8, Peak Infinity Fabric Link Bandwidth 128 GB/s, Passive OAM, Transistor Count 153 Billion. Confirms every numeric field of data/accelerators/amd-instinct-mi325x.json: vram_gb 256, memory_type hbm3e, memory_bus_bit 8192, memory_bandwidth_gbps 6000, tdp_w 1000, and all eleven flops rows. DENSE/SPARSE FLAGS AUDITED ROW BY ROW: every dense flag matches its basis string and every sparse row is exactly 2x. The MI325X page publishes BYTE-IDENTICAL compute rows to MI300X, which independently confirms the record's 'identical compute silicon, only memory and power changed' claim from two separate vendor pages. PCIe: generation and width only, 'PCIe 5.0 x16', NO bandwidth figure published - same situation as MI300X, so the record correctly stores only the pcie-gen5 tag and no host bandwidth. The 128 GB/s is Infinity Fabric per-link bandwidth, not host.