Cambricon MLU370-X8 AIDC accelerator card product page - full specification table (VERBATIM, Chinese)

VERBATIM from cambricon.com catid=406 (板卡型号 MLU370-X8): 'Cambricon MLUarch03', '7nm', 'FP32、FP16、BF16、INT16、INT8、INT4', '256 TOPS (INT8)', '128 TOPS (INT16)', '96 TFLOPS (FP16)', '96 TFLOPS (BF16)', '24 TFLOPS (FP32)', 'LPDDR5', '48GB', '614.4 GB/s', 'x16 PCIe Gen4', 'MLU-Link接口 4 ports, 16 Lanes, 50 Gbps'. Overview prose: '双槽位250w全尺寸智能加速卡' (dual-slot, 250 W, full-height full-length), '整合了两倍于标准思元370加速卡的内存、编解码资源' (integrates twice the memory and codec resources of the standard Siyuan 370 card), '每张加速卡可获得200GB/s的通讯吞吐性能，是PCIe 4.0带宽的3.1倍' (200 GB/s throughput per card, 3.1x PCIe 4.0 bandwidth). Confirms every numeric field of data/accelerators/cambricon-mlu370-x8.json: 7 nm, vram_gb 48, lpddr5, memory_bandwidth_gbps 614.4, tdp_w 250, FP32 24, FP16 96, BF16 96, INT8 256, and the 'other' 128 row = INT16 128 TOPS (schema precision enum has no int16, so 'other' is the correct landing spot). DENSE/SPARSE: Cambricon publishes NO sparsity variant for any figure - the page prints one number per precision with no 'with sparsity' row, so all five dense:true flags are correct by construction rather than by a stated basis, exactly like AMD's vector rows. PCIe: 'x16 PCIe Gen4' with NO bandwidth figure - the page never states a host bandwidth, so the record correctly stores only the pcie-gen4 tag. Cambricon gives no bus width or pin speed for the LPDDR5 either, so 614.4 GB/s cannot be re-derived - the record's basis string already says exactly that. MEDIA: '最高可支持至8K；264路HEVC全高清视频解码；48路HEVC全高清视频编码' (up to 8K; 264-channel HEVC FHD decode; 48-channel HEVC FHD encode); image '最高分辨率16384x16384；8000 Frames/s 全高清图片解码；6000 Frames/s 全高清图片编码'. The accelerator schema has NO media/decoder field, so these decoder/encoder counts are vendor-stated but structurally unrecordable - listed here so the fact is not lost.