Intel Gaudi 3 AI Accelerator Technical Paper Table 8 - Gaudi 2 vs Gaudi 3 OAM memory attributes incl. TDP (VERBATIM)

VERBATIM ROW (p.15), Gaudi 2 OAM then Gaudi 3 OAM: 'Gen4 x 16 | Gen5 x 16', '64 GB/s bidirectional | 128 GB/s bidirectional', '6 x HBM2E | 8 x HBM2E', '96 GB | 128 GB', '2.46 TB/s | 3.7 TB/s', '48 MB | 96 MB', '6.4 TB/s | 19.2 TB/s', '600 W | 900 W'. DISCREPANCY vs records: data/accelerators/intel-gaudi3.json has tdp_w=null and its notes assert 'TDP is not published in the technical paper' - that is WRONG, this table publishes 900 W for the Gaudi 3 OAM, and the same table publishes 600 W for the Gaudi 2 OAM, so data/accelerators/intel-gaudi2.json also has tdp_w=null against a vendor-stated figure. TDP IS published, in this table. SECOND, SEPARATE ISSUE: this table's 'On-die-SRAM BW' column reads 6.4 TB/s (Gaudi 2) and 19.2 TB/s (Gaudi 3), which contradicts Table 1's 'On-die SRAM Bandwidth (read/write) 6.4/6.4 TB/s | 12.8/6.4 TB/s' for the same part. Neither record stores an on-die-SRAM bandwidth field. The body text resolves it: 'a total throughput of up to 19.2 TB/s for L2 accesses and 6.4 TB/s' for L3 - so 19.2 TB/s is the L2 aggregate and 12.8 TB/s is the L2 read/write number in Table 1. Two different quantities under similar labels in one paper; anyone deriving a roofline from Table 8's SRAM BW row would be off by ~2x. PCIe: independently prints 'bidirectional' as the label, corroborating Table 1's convention. HBM stack counts 6 (Gaudi 2) / 8 (Gaudi 3) are vendor-stated and not stored in the records.