AMD Radeon Instinct MI50 datasheet (archived AMD PDF) - MI50 figures are dense, no structured-sparsity footnote on this generation

VERBATIM 2026-10-04, retrieved with curl and parsed with pymupdf (2 pages). Separate from w4h-amd-radeon-instinct-mi60-datasheet because accelerators/amd-radeon-instinct-mi50x is a distinct record and this document's numbers for MI50 are what that record rests on. VERBATIM PROSE: 'Delivering up to 26.5 TFLOPS of native half-precision (FP16) or up to 13.3 TFLOPS single-precision (FP32) peak floating point performance and INT8 support and combined with 16GB or 32GB of high-bandwidth HBM2 ECC memory'. Also 'The Radeon Instinct MI50 delivers great double precision performance with up to 6.6 TFLOPS FP64 performance' and 'With 16GB or 32GB HBM2 memory utilizing a four-stack memory configuration, the new AMD Radeon Instinct MI50 delivers ultra-high memory bandwidth with up to 1 TB/s memory bandwidth'. VERBATIM FOOTNOTE 1 (the only footnote on the sheet): 'As of Jun 19, 2019. Radeon Instinct MI50 and MI60 "Vega 7nm" technology-based accelerators support PCIe Gen 4.0 providing up to 64 GB/s peak theoretical transport data bandwidth from CPU to GPU per card. Previous Gen Radeon Instinct compute GPU cards are based on PCIe Gen 3.0 providing up to 32 GB/s peak theoretical transport data bandwidth.' SPARSITY CONVENTION - VERBATIM NEGATIVE: this footnote is about PCIe generation, not sparsity, and the document contains NO sparsity footnote, NO 'with Structured Sparsity' row title, and the strings 'sparse'/'sparsity' do not occur. Under AMD's rule (sparsity is labelled only on rows explicitly titled 'with Structured Sparsity'; a row without that title is dense) every figure here is DENSE as published and must NOT be halved: FP16 26.5 TFLOPS, FP32 13.3 TFLOPS, FP64 6.6 TFLOPS, memory bandwidth up to 1 TB/s. WHY THE GENERATION MATTERS AND WHY THE ABSENCE IS NOT A CARELESSNESS: AMD's 'with Structured Sparsity' footnote convention arrives with the Instinct MI100 generation and later. On MI50/MI60 there is no structured sparsity to describe, so there is no footnote to print and no doubled figure to halve. Any pipeline that applies AMD's MI300-era halving rule uniformly across all AMD parts will corrupt these two records and will do so silently, because a halved 26.5 is 13.25, which still looks like a plausible TFLOPS value. DISAGREEMENT WITHIN AMD, RECORDED NOT RESOLVED: the archived MI60 product page's related-products block gives the MI50 as 'Peak Half Precision (FP16) Performance: 26.8 TFLOPs' and 'Peak Single Precision (FP32) Performance: 13.4 TFLOPs' where this datasheet says 26.5 and 13.3. See w4h-amd-radeon-instinct-mi60-datasheet for the same figure quoted from the other side. The stored MI50X record carries the datasheet values.