AMD Radeon Instinct MI60 datasheet (archived AMD PDF) - MI60 and MI50 compute table, no sparsity labelling at all

VERBATIM 2026-10-04, retrieved with curl and parsed with pymupdf (2 pages). The URL is AMD's own original PDF path, reached through the Wayback Machine because AMD no longer serves it. Recorded because accelerators/amd-radeon-instinct-mi60 cites an archived PRODUCT PAGE rather than this datasheet, and this datasheet is the document that prints the compute table. PERFORMANCE TABLE, verbatim: 'PERFORMANCE | Compute Units 64 | Stream Processors 4,096 | Peak INT8 Up to 59.0 TOPS | Peak FP16 Up to 29.5 TFLOPS | Peak FP32 Up to 14.7 TFLOPS | Peak FP64 Up to 7.4 TFLOPS | Bus Interface PCIe Gen 3 and Gen 4 Capable'. MEMORY, verbatim: '32GB HBM2 | 4,096-Bits | 1 GHz | Up to 1 TB/s' under 'Memory Size / Memory Interface / Memory Clock / Memory Bandwidth'. BOARD, verbatim: 'Full-Height, Dual Slot | 10.5" Long | Passively Cooled | 300W TDP'. SPARSITY CONVENTION - VERBATIM NEGATIVE, AND THIS IS THE FINDING: the strings 'sparse' and 'sparsity' DO NOT OCCUR ANYWHERE IN THIS DOCUMENT. Not once, in prose or in the performance table. There is no row titled 'with Structured Sparsity', no sparse/dense pair, and no halving note. Under AMD's documented convention - sparsity is labelled ONLY on rows explicitly titled 'with Structured Sparsity', and a row without that title is dense - every figure on this sheet is DENSE as published: FP16 29.5 TFLOPS, FP32 14.7 TFLOPS, FP64 7.4 TFLOPS, INT8 59.0 TOPS. Halving any of them is an error. This is the earliest-generation Instinct part to predate AMD's structured-sparsity footnote convention entirely, which is why the absence here is expected rather than surprising - but it still has to be checked, because the absence is what makes the figure dense and an unchecked absence is indistinguishable from an unchecked halving. CROSS-CHECK AGAINST THE ARCHIVED MI60 PRODUCT PAGE (source amd-mi60-product-page, read 2026-10-04): the product page's GPU Specifications table reads 'Peak Half Precision (FP16) Performance 29.5 TFLOPs | Peak Single Precision (FP32) Performance 14.7 TFLOPs | Peak Double Precision (FP64) Performance 7.4 TFLOPs | Peak INT8 Performance 58.9 TFLOPs'. The datasheet says 'Up to 59.0 TOPS' where the product page says '58.9 TFLOPs'. Note the UNIT as well as the value: the datasheet calls INT8 a TOPS figure and the product page calls the same quantity TFLOPs. The stored record value of 58.9 matches the PRODUCT PAGE, not this datasheet. That is a 59.0-vs-58.9 rounding difference plus a TOPS/TFLOPs unit inconsistency inside AMD's own documents; it is recorded rather than resolved, because no source states which is the intended precision of the last digit. ALSO IN THE PRODUCT PAGE, IN THE RELATED-PRODUCTS BLOCK, VERBATIM, for the MI50: 'Compute Units: 60 | Stream Processors: 3840 | Peak Half Precision (FP16) Performance: 26.8 TFLOPs | Peak Single Precision (FP32) Performance: 13.4 TFLOPs | Peak Double Precision (FP64) Performance: 6.7 TFLOPs | Memory Size: 16 GB | Memory Type (GPU): HBM2 | Memory Bandwidth: 1024 GB/s'. The archived MI50 datasheet (source amd-mi50-datasheet) instead says 'up to 26.5 TFLOPS of native half-precision (FP16) or up to 13.3 TFLOPS single-precision (FP32)'. So AMD's own MI50 numbers disagree between documents: 26.8/13.4 (product page) versus 26.5/13.3 (datasheet). The stored MI50X record carries 26.5 FP16 and 13.3 FP32, i.e. the datasheet figures. Both are dense, per the same absence-of-sparsity-labeling reasoning.