Huawei Atlas 650E AI server product page - AI Performance and on-chip memory tables, SERVER-level figures only

VERBATIM 2026-10-04 via web_extract. Recorded because accelerators/huawei-ascend-950dt derives all of its per-NPU figures by dividing Huawei's server figures by 8, and this is the server document that licence rests on. Re-read row by row to check the derivation. PRODUCT FEATURES, verbatim: 'The Atlas 650E server, powered by eight 950DT NPUs, delivers up to 12.4 PFLOPS @ mxFP4. It features Huawei's self-developed on-chip memory with up to 4.0 TB/s R/W bandwidth while supporting 16-NPU full-mesh via UnifiedBus Link 2.0 protocol.' And under headings: 'MXFP4 Low-precision Inference | 12.4PFLOPS · MXFP4 compute power | Achieve industry-leading compute performance of 12.4 PFLOPS @ mxFP4 | Support HiF8 / mxFP8 / mxFP4 data formats'; 'Ultra-high Memory Bandwidth | 4.0TB/s · On-chip memory bandwidth | Deliver industry-leading memory R/W bandwidth of 4.0 TB/s | 768 GB on-chip memory per server'; 'Ultra-high UB Link Bandwidth | 16NPUs· Ultra-high interconnect bandwidth | Provide 13.4 TB/s UB Link bandwidth per server (16-NPU FM) | Support 16-NPU UB full-mesh interconnect across 2 servers'. 'Atlas 650E Product Specifications' TABLE, verbatim: 'Form Factor | 14U AI server' 'NPU | 8 × 950DT NPU' 'CPU | 2 × 950 CPU (up to 96 cores, 2.3GHz)' '*AI Performance | 12.48 PFLOPS mxFP4 6.43 PFLOPS mxFP8/FP8/HiF8 3.40 PFLOPS FP16/BF16' 'On-chip Memory | 8 × 96 GB total, 4.0 TB/s peak memory bandwidth' 'System Memory | Support 24 memory slots running at up to 6,400 MT/s Support up to 64 GB per DDR5 RDIMM' 'Storage | 8 x 2.5 NVMe + 2 x 2.5 SATA (with RAID card configured)' 'UB Link Bandwidth | 8-NPU Server: 8 x 784 GB/s (bidirectional)' PRECISION WORDING, WHICH IS THE POINT: the precisions are printed as 'mxFP4', 'mxFP8/FP8/HiF8' and 'FP16/BF16'. Note that the 6.43 figure is a SINGLE number covering THREE named formats (mxFP8, FP8, HiF8), and that there is no separate HiF8 row. SPARSITY/DENSE CONVENTION, VERBATIM NEGATIVE: this page carries NO footnote, NO 'with Structured Sparsity' label, NO sparse/dense pair and NO dense-or-sparse marker of any kind on the AI Performance row. Huawei does not print a sparsity convention here at all, so the figures must be recorded as published with no halving and no doubling applied - there is no document in which to find a rule that would license either. DISCLAIMER, VERBATIM: '*Product images are for reference only.' and Huawei's standing theoretical-power caveat, which appears on the companion cluster page: '*Theoretical computing power may have a <1% error in actual testing.' DERIVATION AUDIT (this is why the record exists). The stored per-NPU values in accelerators/huawei-ascend-950dt are 12.48/8 = 1.56 PFLOPS = 1,560 TFLOPS mxFP4; 6.43/8 = 0.80375 PFLOPS = 803.75 TFLOPS; 3.40/8 = 0.425 PFLOPS = 425 TFLOPS. The arithmetic is correct as stated and the divisor of 8 matches the page's own 'NPU 8 × 950DT NPU'. However the fp16/bf16 rows are recorded with basis vendor-spec-sheet while being per-NPU derivations from a server figure, and the fp4 row is correctly recorded with basis derived. That is an internal inconsistency in basis between three rows that come from the same division of the same table: only the fp4 row is labelled derived. The fp16, bf16 and fp8 rows should also be basis derived, or the 950DT record's basis_detail should state why they are not. MEMORY BANDWIDTH: '8 × 96 GB total, 4.0 TB/s peak memory bandwidth' is a single SERVER aggregate, so the stored per-NPU 500 GB/s (= 4.0/8) is likewise a derivation and its memory_bandwidth_basis already says so honestly. 'On-chip Memory' is the page's own term - this is NOT HBM and must not be compared to an HBM bandwidth figure without saying so. The stored memory_type 'on-chip memory (Huawei-developed; not HBM)' is consistent with the vendor wording.