Iluvatar CoreX Tiangai 100 (BI-V100) and Zhikai 100 (MR-V100) product pages - memory/interface/TDP published, NO compute figure published
Fields
sources/w4h-iluvatar-tiangai100-zhikai100-spec-tablesNotes
VERBATIM 2026-10-04 via web_extract of BOTH the Tiangai 100 (BI-V100) training-card page and the Zhikai 100 (MR-V100) inference-card page, which the first page links as 智铠推理系列. Recorded because accelerators/iluvatar-bi-v100-mr-v100 cites both pages but has an EMPTY flops array; this source establishes that the empty array is correct, and corrects the record's memory type.
TIANGAI 100 (BI-V100) '产品规格 / PRODUCT SPECIFICATIONS' TABLE, verbatim, all rows: '软件生态 | 兼容主流通用计算软件框架 支持主流深度学习开发框架' '散热方式 | 被动散热' '尺寸 | 全长全高双槽 PCIe 卡,兼容主流服务器' '功耗 | 板级功耗 250W' '接口 | PCIe Gen4.0 x 16 lane 共享 64 GB/s 主控双向带宽 共享 64 GB/s 片间互联带宽' '内存 | 32 GB DRAM HBM2' '架构 | 通用GPU' '型号 | 天垓100加速卡(BI -V100)'
ZHIKAI 100 (MR-V100), verbatim: '尺寸 | 半长半高单槽 PCle 卡 / 全长全高单槽 PCle' (two variants), '功耗 | 板级功耗 75W / 板级功耗 150W', '接口 | PCle Gen4.0 X 16 lane', '内存 | 16 GB HBM2E / 32 GB HBM2E', '型号 | 智铠50加速卡(MR-V50) / 智铠100加速卡(MR-V100)'. Note the Zhikai page covers TWO cards in one table: MR-V50 at 16 GB HBM2E / 75 W and MR-V100 at 32 GB HBM2E / 150 W. Both are HBM2E.
MEMORY TYPE, VERBATIM AND IT CORRECTS A STORED VALUE: the Tiangai 100 row reads '内存 | 32 GB DRAM HBM2' - 'DRAM HBM2'. The Zhikai page says plainly 'HBM2E' for both of its cards, with no 'DRAM' prefix. So the two cards in the combined record do NOT share a memory type: Tiangai 100 is printed as HBM2 (with the odd 'DRAM' prefix) and Zhikai 100 is printed as HBM2E. The stored accelerators/iluvatar-bi-v100-mr-v100 memory_type is the single value 'hbm2e' for both, which matches Zhikai but not Tiangai.
MEMORY BANDWIDTH: NEITHER PAGE PUBLISHES A BANDWIDTH FIGURE. The '64 GB/s' values on the Tiangai page are explicitly NOT memory bandwidth - they are '共享 64 GB/s 主控双向带宽' (64 GB/s shared bidirectional host bandwidth) and '共享 64 GB/s 片间互联带宽' (64 GB/s shared die-to-die interconnect bandwidth), i.e. host and chip-to-chip links. The stored memory_bandwidth_gbps is already null, which is CORRECT, and this source is the reason it can stay null.
NEGATIVE FINDING - NO COMPUTE FIGURE: NEITHER page publishes any TFLOPS, TOPS or numeric compute figure. The Tiangai feature prose says '提供业界领先的高算力和高能效比' (industry-leading compute power and energy efficiency) with no number, and '在百余个算法模型的测试平均性能可媲美主流产品' (average performance across 100+ algorithm models comparable to mainstream products) - also unquantified. The Zhikai page says '支持FP32、FP16、INT8等多精度推理混合计算... 相较于市场上现有主流产品,智铠100将提供2-3倍的实际使用性能' (2-3x the actual performance of existing mainstream products) - a RELATIVE claim about actual performance, not an absolute compute figure. So accelerators/iluvatar-bi-v100-mr-v100's empty flops array is CORRECT.
SPARSITY/DENSE CONVENTION: no sparsity footnote, no 'with Structured Sparsity' title, no sparse/dense pair on either page; the strings 'sparse'/'sparsity' do not occur. Recorded so that no figure is later halved on the assumption that Iluvatar follows AMD's or NVIDIA's convention.
BI-V150 (Tiangai 150), READ THE SAME PASS for the record: https://www.iluvatar.com/productDetails?fullCode=cpjs-yj-xlxl-tg150 publishes as its only numeric specification, in the feature prose: '配备了64GB的HBM内存,板级功耗为350W' (equipped with 64GB of HBM memory, board-level power consumption 350W). NO compute figure and NO memory bandwidth. So accelerators/iluvatar-bi-v150, whose only source is the mirrorfrog.com aggregator page, has a VENDOR page available that publishes 64 GB HBM and 350 W board power - both of which the record currently lacks - and that page should replace the aggregator for those two fields. accelerators/iluvatar-bi-v250 shares that same single aggregator source; no BI-V250 product page was located on iluvatar.com during this pass, and that absence is recorded rather than assumed.
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