verifiedhigh · 0.90updated 2026-10-04

Intel Data Center GPU Flex Series product brief (Flex 140 / Flex 170 peak-compute table)

spec-sheet

Fields

sources/w4h-intel-dc-gpu-flex-series-product-brief

URL

https://cdrdv2-public.intel.com/768797/intel-data-center-gpu-flex-series-product-brief-final.pdf

Publisher

Intel Corporation (cdrdv2-public.intel.com, Intel's own document CDN)

Kind

spec-sheet

Published

2022-08

Accessed

2026-10-04

Archived URL

https://www.intel.com/content/www/us/en/products/details/discrete-gpus/data-center-gpu/flex-series.html

notes

VERBATIM 2026-10-04, retrieved with curl -L -A "Mozilla/5.0 (Windows NT 10.0; Win64; x64) AppleWebKit/537.36 Chrome/126 Safari/537.36" and parsed with pymupdf (document footer '0822/MH/MESH/349353-001US'). This is the ONLY Intel first-party document found that states Flex 170 compute figures. COMPARISON TABLE, two columns 'Intel® Data Center GPU Flex 140' then 'Intel Data Center GPU Flex 170', verbatim: 'Card Form Factor | Half height, half length, single wide, passive cooling | Full height, three-quarter length, single wide, passive cooling' 'Card TDP | 75 watts | 150 watts' 'GPUs per Card | 2 | 1' 'GPU Microarchitecture | Xe HPG | Xe HPG' 'Xe Cores | 16 (8 per GPU) | 32' 'Media Engine | 4 (2 per GPU) | 2' 'Peak Compute (Systolic) | 8 TFLOPS (FP32) / 105 TOPS (INT8) | 16 TFLOPS (FP32) / 250 TOPS (INT8)' 'Memory Type | GDDR6 | GDDR6' 'Memory Capacity | 12 GB (6 per GPU) | 16 GB' 'Virtualization (Instances) | 3 SR-IOV (62) | SR-IOV (31)' SPARSITY CONVENTION, VERBATIM: THE ROW IS TITLED 'Peak Compute (Systolic)' AND ITS PRECISION IS NAMED INLINE, '(FP32)' AND '(INT8)'. There is NO sparsity footnote in this document, NO 'with Structured Sparsity' title, and NO sparse/dense pair. Intel's stated convention is that sparsity is labelled only on rows explicitly titled for it, and this row is not titled for it, so 16 TFLOPS FP32 and 250 TOPS INT8 are DENSE as printed and must NOT be halved. Confirmed by inspection of the full text of the PDF: the strings 'sparse' and 'Sparsity' do not occur. COLUMN TRAP, WHICH IS THE LIKELY ORIGIN OF AN ERROR ELSEWHERE IN THE REPO: this brief covers TWO parts whose figures differ by almost exactly two, because the Flex 140 is a dual-GPU card. Flex 140 = 75 W, 8 TFLOPS FP32, 105 TOPS INT8, 16 Xe cores, 12 GB. Flex 170 = 150 W, 16 TFLOPS FP32, 250 TOPS INT8, 32 Xe cores, 16 GB. A record that mixes a Flex 170 core count with a Flex 140 TDP, or vice versa, will look internally plausible because the two parts share a name.

Notes

SPARSITY CONVENTION, VERBATIM: THE ROW IS TITLED 'Peak Compute (Systolic)' AND ITS PRECISION IS NAMED INLINE, '(FP32)' AND '(INT8)'. There is NO sparsity footnote in this document, NO 'with Structured Sparsity' title, and NO sparse/dense pair. Intel's stated convention is that sparsity is labelled only on rows explicitly titled for it, and this row is not titled for it, so 16 TFLOPS FP32 and 250 TOPS INT8 are DENSE as printed and must NOT be halved. Confirmed by inspection of the full text of the PDF: the strings 'sparse' and 'Sparsity' do not occur. COLUMN TRAP, WHICH IS THE LIKELY ORIGIN OF AN ERROR ELSEWHERE IN THE REPO: this brief covers TWO parts whose figures differ by almost exactly two, because the Flex 140 is a dual-GPU card. Flex 140 = 75 W, 8 TFLOPS FP32, 105 TOPS INT8, 16 Xe cores, 12 GB. Flex 170 = 150 W, 16 TFLOPS FP32, 250 TOPS INT8, 32 Xe cores, 16 GB. A record that mixes a Flex 170 core count with a Flex 140 TDP, or vice versa, will look internally plausible because the two parts share a name.

Cross-references

This record references no other records.