NVIDIA Blackwell datasheet (GB200 NVL72 / GB200 NVL4 / HGX B200) - every Tensor Core row printed sparse-only, retrieved and re-read row by row

VERBATIM 2026-10-04, retrieved with curl and parsed with pymupdf. HOST CAVEAT, WHICH IS THE REASON THIS RECORD EXISTS ALONGSIDE THE FIRST-PARTY ONE: the existing source vb-nvidia-blackwell-datasheet-firstparty already carries NVIDIA's OWN hosted copy of this document at dam-cdn.nvd.orangelogic.com, so this record is deliberately NOT presented as better evidence. Its purpose is narrower - it is the row-by-row re-read of the HGX B200 column against the dense/sparse footnotes, because the B200 record's column attribution was previously wrong (see the discrepancy list) and re-reading the reseller copy is how the error was found. The spec text of the reseller copy and the first-party copy was compared on the Technical Specifications table and is IDENTICAL, including the 'PLFOPS'-style typos, which is itself evidence they are the same document. TECHNICAL SPECIFICATIONS1 table, columns 'GB200 NVL72 | GB200 NVL4 | HGX B200', verbatim: 'NVIDIA Blackwell GPUs | Grace CPUs | 72 | 36 4 | 2 8 | 0' 'CPU Cores | 2,592 Arm Neoverse V2 Cores | 144 Arm Neoverse V2 Cores | -' 'Total NVFP4 Tensor Core2 | 1,440 | 720 PFLOPS | 80 | 40 PFLOPS | 144 | 72 PFLOPS' 'Total FP8/FP6 Tensor Core2 | 720 PFLOPS 40 PFLOPS 72 PFLOPS' 'Total Fast Memory | 31 TB | 1.8 TB | 1.4 TB' 'Total Memory Bandwidth | 576 TB/s | 32 TB/s | 62 TB/s' 'Total NVLink Bandwidth | 130 TB/s 7.2 TB/s | 14.4 TB/s' 'FP4 Tensor Core2 | 20 PFLOPS 20 PFLOPS 18 PFLOPS' 'FP8/FP6 Tensor Core2 | 10 PFLOPS 10 PFLOPS 9 PFLOPS' 'INT8 Tensor Core2 | 10 POPS 10 POPS 9 POPS' 'FP16/BF16 Tensor Core2 | 5 PFLOPS 5 PFLOPS 4.5 PFLOPS' 'TF32 Tensor Core2 | 2.5 PFLOPS 2.5 PFLOPS 2.2 PFLOPS' 'FP32 | 80 TFLOPS 80 TFLOPS 75 TFLOPS' 'FP64/FP64 Tensor Core | 40 TFLOPS 40 TFLOPS 37 TFLOPS' 'GPU Memory | Bandwidth | 186 GB HBM3E | 8 TB/s | 186 GB HBM3E | 8 TB/s | 180 GB HBM3E | 7.7 TB/s' 'Max Thermal Design Power (TDP) | Configurable up to 1,200 W | Configurable up to 1,200 W | Configurable up to 1,000 W' 'Interconnect | Fifth-generation NVLink: 1.8 TB/s PCIe Gen5: 128 GB/s' [sic: 'INT8 Tensor Core2 10 POPS' is NVIDIA's printed text on this sheet - 'POPS', not 'TOPS'. Reproduced verbatim.] FOOTNOTES, VERBATIM: footnote 1: 'Specifications in sparse | dense.' footnote 2: 'Specifications in sparse. Dense is one-half of the sparse spec shown.' WHICH CONVENTION APPLIES TO WHICH ROW: on this sheet EVERY Tensor Core row carries footnote 2 - the sparse-only, halving convention - including 'FP4 Tensor Core2' and the 'Total NVFP4 Tensor Core2' system row. This is the crucial difference from the Blackwell ULTRA sheet, where the FP4 row instead carries footnote 1, the labelled Sparse|Dense pair. The two sheets are near-identical in layout and differ precisely on the row the repo is most likely to get wrong. CONSEQUENCE FOR THE HGX B200 COLUMN, DENSE AS PUBLISHED: FP4 18 PFLOPS -> 9 PFLOPS dense = 9,000 TFLOPS; FP8/FP6 9 -> 4.5 PFLOPS dense = 4,500 TFLOPS; FP16/BF16 4.5 -> 2.25 PFLOPS dense = 2,250 TFLOPS; TF32 2.2 -> 1.1 PFLOPS dense = 1,100 TFLOPS. FP32 75 TFLOPS and FP64 37 TFLOPS carry no marker and are dense as printed. CONSEQUENCE FOR THE GB200 NVL72 COLUMN, DENSE AS PUBLISHED: FP4 20 -> 10 PFLOPS; FP8/FP6 10 -> 5 PFLOPS; FP16/BF16 5 -> 2.5 PFLOPS; TF32 2.5 -> 1.25 PFLOPS; FP32 80 and FP64 40 unmarked and dense. SELF-CONSISTENCY CHECK THAT SETTLES THE COLUMN QUESTION: 8 GPUs x 18 PFLOPS sparse = 144 PFLOPS, which is exactly the 'Total NVFP4 Tensor Core2 144 PFLOPS' printed in the HGX B200 column of the same table; and 8 x 9 PFLOPS dense = 72 PFLOPS, matching the second figure of that same pair '144 | 72 PFLOPS'. The GB200 NVL72 pair '1,440 | 720 PFLOPS' is 72 x 20 and 72 x 10. So the GB200 system row is ALSO a sparse|dense pair here, printed under footnote 2, with the pair already expanded. A reader who takes '144 PFLOPS' as dense gets a figure 2x the dense per-GPU number on the same sheet.