Rebellions Rebel100 accelerator card brochure v1.6 (the document that prints the explicit '(Dense)' compute label)

VERBATIM 2026-10-04 via web_extract of the PDF linked from the 'Download Brochure' button on https://rebellions.ai/rebellions-product/rebel100/ . accelerators/rebellions-rebel100 cites the PRODUCT PAGE; this brochure is the document that actually prints the compute label, and it settles the dense/sparse question that the product page leaves implicit. SPEC TABLE, verbatim: 'Architecture | 4-homogeneous-chiplet SoC based on UCIe-Advanced | Compute (Dense) | 1,024 TFLOPS (FP16) | 2,048 TFLOPS (FP8) | Memory | HBM3E 144GB | 4.8TB/s | Interconnection | 2x PCIe Gen5 x16 | External Memory Chiplet (UCIe-A) | 16Gbps 1TB/s per channel | Host Connection | Up to 600W Power Consumption | Software | Native-support of PyTorch 2.x, vLLM and Triton'. SPARSITY CONVENTION, VERBATIM AND UNAMBIGUOUS: the compute block is headed 'Compute (Dense)' and the two figures sit under that single heading. The document prints NO sparse figure anywhere, NO 'one-half' relationship, and NO sparse/dense pair. Therefore 1,024 TFLOPS FP16 and 2,048 TFLOPS FP8 are DENSE as printed and must NOT be halved. This is a THIRD convention, distinct from both the NVIDIA 'Dense is one-half of the sparse spec shown' and the NVIDIA 'Specification in Sparse | Dense' pair, and distinct from AMD's 'only rows titled with Structured Sparsity'. Rebellions simply labels the block 'Compute (Dense)' and prints one number per precision. The stored record values (fp16 1024 dense:true, fp8 2048 dense:true) are CORRECT against this document and are here independently confirmed. OTHER FIGURES VERBATIM: 'Built to serve frontier LLMs with high utilization and lo[w power]', 'At its core is a modular SoC that fuses four identical compute chiplets into a monolithic-acting unit via high-bandwidth UCIe-Advanced links', 'A mixed-precision core with per-operand flexibility supports FP8 and FP16 in a unified pipeline-eliminating instruction switching and boosting compute density by x2.8', 'A pre-compiled DMA engine orchestrates KV cache access with command-level bandwidth and QoS control, delivering x3.3 higher per-core bandwidth-keeping 32K-token decoding smooth', 'Four chiplets are unified via 1TB/s per-channel UCIe-Advanced links', 'In internal evaluations, Rebel100 has demonstrated higher throughput than NVIDIA H200-class GPUs'. DISCLAIMER, VERBATIM: 'All information is provided "as is" without any warranties or guarantees by Rebellions, Inc. Rebellions assumes no liability for use of or reliance upon this information.' And: 'Disclaimer: All performance data is based on Rebellions' internal estimates and tests under optimized settings. GPU figures are based on public data or third-party benchmarks. Actual results may vary depending on system conditions and software versions. This information is for reference only and subject to change without notice.' The H200-comparison claim is therefore an internal estimate, not a measured third-party result, and should not be filed as a benchmark.