Rebellions Rebel100 brochure PDF v1.6 - the '16Gbps' sits in the 'Chiplet Interface (UCIe-A)' block, confirming it is NOT a DRAM pin rate

CONFIRMS THE REJECTION OF A FABRICATED memory_bus_bit, WITH THE DOCUMENT'S OWN LAYOUT AS THE EVIDENCE. data/accelerators/rebellions-rebel100 correctly holds memory_bus_bit null, and its note explains that dividing the brochure's 4.8TB/s by the brochure's '16Gbps' would yield 2400 bits, which is not a real HBM interface width. This source record attaches the proof. THE BROCHURE'S SPEC BLOCK, verbatim, with the field grouping intact (the PDF text extraction preserves the label/value pairing): Architecture 4-homogeneous-chiplet SoC based on UCIe-Advanced Compute (Dense) 1,024 TFLOPS (FP16) 2,048 TFLOPS (FP8) External Memory HBM3E 144GB 4.8TB/s Chiplet Interface (UCIe-A) 16Gbps 1TB/s per channel Host Connection 2x PCIe Gen5 x16 Power Consumption Up to 600W Software Native-support of PyTorch 2.x, vLLM and Triton The identical block appears on the product page https://rebellions.ai/rebellions-product/rebel100/ under the headings 'External Memory / HBM3E 144GB 4.8TB/s' and 'Chiplet Interface (UCIe-A) / 16Gbps 1TB/s per channel', so the grouping is not an artifact of one PDF renderer. '16Gbps' is printed INSIDE THE BLOCK LABELLED 'Chiplet Interface (UCIe-A)', adjacent to '1TB/s per channel', and it is separated from 'HBM3E 144GB 4.8TB/s' by a field boundary. It therefore describes the external UCIe-A memory chiplet link, not the HBM3E DRAM interface. The arithmetic settles it independently: 4800 GB/s / 16 Gbps/pin = 2400 bits, and no HBM generation has a 2400-bit bus (HBM2 = 1024, HBM2E = 1024, HBM3 = 1024, HBM3E = 1024 per stack). A derivation that produces an interface width no generation of the memory it claims to describe is a derivation that has picked up the wrong denominator. SECOND, INDEPENDENT CONFIRMATION OF THE SAME CONCLUSION: the product page's prose describes the on-package interconnect as 'offering 1TB/s per channel bi-directional bandwidth with just 11ns latency' and the chiplets as unified 'via 1TB/s per-channel UCIe-Advanced links', with '16Gbps' never once tied to HBM in prose either. THE COMPUTE FIGURES ARE FINE, AND DENSE: 'Compute (Dense)' is the vendor's own explicit label, so fp16 1024 and fp8 2048 are genuinely dense and vendor_claim true is correct. The brochure adds '1,024 TFLOPS (FP16)' with a thousands separator - worth noting because a naive numeric match against '1024' fails on the comma and would have manufactured a false citation failure. It also states 'no stalls in sparse or imbalanced workloads' and that a hardware sync fabric 'coordinates execution across chiplets, including sparse and MoE models' - sparse MODELS, not a sparse-compute footnote, so the dense label is not contradicted by the word 'sparse' appearing elsewhere on the page. The brochure's benchmark claim is explicitly self-described as marketing: 'Rebel100 has demonstrated higher throughput than NVIDIA H200-class GPUs on large-scale LLMs', with the disclaimer 'All performance data is based on Rebellions' internal estimates and tests under optimized settings. GPU figures are based on public data or third-party benchmarks.' Benchmark condition given verbatim: 'Performance measured on Llama 3.3 70B (TP2, FP8) with runtime input/output length 2048/2048.'