AMD EPYC 9755 product page - per-socket fabric figures published as PCIe width and memory bandwidth only (verified negative)

VERIFIED NEGATIVE for the HOST-SIDE / CPU-side Infinity Fabric generations, recorded so the gap is not silently filled by inference. The EPYC 9755 connectivity block publishes: 'PCI Express(R) Version: PCIe(R) 5.0 x128', 'Memory Channels: 12', 'System Memory Specification: Up to 6400 MT/s', 'Per Socket Mem BW: 614 GB/s', and Supported Technologies 'AMD Infinity Guard , AMD Infinity Architecture'. It publishes NO Infinity Fabric link count and NO per-link Infinity Fabric bandwidth - the same is true of the EPYC 9004 and 9005 series pages checked. AMD's consumer-facing 'Infinity Architecture' technology page and the EPYC 9004/9005 product briefs were also checked and state no per-generation IF link rate. CONSEQUENCE: the CPU-to-CPU / CPU-to-device Infinity Fabric generations (Zen through Zen 5) cannot be given per-link bandwidth figures from these product pages, and the EPYC pages' 'Per Socket Mem BW: 614 GB/s' is DDR5 MEMORY bandwidth, NOT an Infinity Fabric figure - substituting it for one would be exactly the kind of conflation this repo has been corrupted by before. The host-side per-generation IF rates remain unrecorded here.