Cloud TPU v3 system architecture

Per-pod figures for the last 2D-torus generation before v4: 1024-chip pod, 2D torus, all-reduce 340 TB/s, bisection 6.4 TB/s, 123 TFLOPS bf16 per chip, 32 GiB HBM2 at 900 GBps. Publishes NO per-chip ICI bandwidth figure, which is why the v3 interconnect record carries pod-level all-reduce and bisection only. Page lists supported accelerator types v3-8 through v3-2048.