HipKittens README (HazyResearch) - AMD port of the ThunderKittens primitives

The AMD half of the ThunderKittens story and the clearest published statement of what does NOT port between CUDA and ROCm at the kernel-DSL level. 'We explore whether the primitives used in prior DSLs (like TK) suffice for AMD, or whether we need entirely new primitives. We find that core tile and bulk compute interfaces carry over from TK to HK, but decisions around memory access patterns, scheduling compute and memory, and ordering thread blocks within the chiplet architecture differ.' Chiplet-aware thread-block ordering has no NVIDIA analogue and is exactly the thing a straight port cannot express. Supported hardware: CDNA3 and CDNA4. Dated facts: accepted to MLSys 2026 (January 2026), presented as a GPU Mode lecture (February 2026), and - the deployment-relevant one - 'March 2026: HipKittens is officially an AITER backend', i.e. it is inside AMD's own inference kernel library rather than beside it. MIT.