Cerebras CS-4 page read in full - WSE-3 Turbo per-wafer figures, three wafers per system, Nexus platform, 2 us wafer-to-wafer latency

The repo already held asic-cerebras-cs4 with a one-line summary; this record captures the full page text read 2026-10-05, because the CS-4 / WSE-3 Turbo record was added in this pass and the earlier summary did not distinguish per-wafer figures from per-system figures. VERBATIM: 'Three WSE-3 Turbos per System' / 'Each wafer delivers up to 2x the speed of the previous generation'. 'CS-4 runs on WSE-3 Turbo-the world's largest and fastest AI processor. Its four trillion transistors and 900,000 AI cores deliver 250 PFLOPS of compute and 43.2 petabytes per second of memory bandwidth.' 'Twice the compute. Twice the bandwidth. Less than half the latency.' 'By reducing wafer-to-wafer interconnect latency to 2 microseconds, CS-4 delivers more than 1,000 tokens per second on models exceeding 50 trillion parameters'. 'up to 10x more throughput per watt than CS-3 while generating tokens up to 30x faster than production GPU systems'. 'First CS-4 shipments begin this quarter.' 'CS-4 is the first system built on the Cerebras Nexus Platform Architecture.' 'With power delivery just 0.5 millimeters away from the processor - roughly 100x closer than the roughly 50mm of conventional GPU boards - CS-4 nearly eliminates board-level power loss. This enables the delivery of twice as much power to the WSE-3T, enabling higher operating frequencies.' 'Next-gen wafer I/O ... The Wafer I/O Module also enables wafers to be linked within and across racks without a switch, for wafer-to-wafer latency as low as two microseconds'. THE PER-WAFER vs PER-SYSTEM DISTINCTION, which is the whole reason this source record exists: 250 PFLOPS and 43.2 PB/s are stated as properties of the WAFER ('Its four trillion transistors and 900,000 AI cores deliver 250 PFLOPS'), and the system is THREE wafers. So a per-wafer record stores 250 PFLOPS and 43200 GB/s, and a per-system total would be 750 PFLOPS and 129.6 PB/s. The page publishes NO system total, so none is recorded. Anyone dividing the wafer figures by three, or multiplying them by three into a chip field, is making an inference the page does not support. THE FIGURES THAT ARE NOT PUBLISHED ANYWHERE ON THIS PAGE, and are therefore null in the record rather than guessed: on-wafer SRAM CAPACITY for the WSE-3T (the 43.2 PB/s bandwidth is given, the capacity is not - see vb-cerebras-wse3t-250pf, which records the same absence on the /chip page), memory bus width (structurally inapplicable - there is no DRAM tier), TDP, and process node. The page's '30x faster than GPUs', '10x throughput per watt' and '1,000 tokens per second on models exceeding 50 trillion parameters' are marketing comparisons against an unnamed GPU baseline and are not used as numbers in the record. VENDOR DISCLAIMER, VERBATIM, which is why every comparative claim on this page is treated as a vendor claim: 'Performance comparisons are based on third-party benchmarking or internal testing. Observed inference speed improvements versus GPU-based systems may vary depending on workload, configuration, date and models being tested.'