d-Matrix Corsair white paper read in full - per-card and per-server Capacity Memory figures, MXINT16 row, DIMC architecture

The repo held this PDF as a source with EMPTY notes (source d-matrix-corsair-white-paper: notes was the empty string, confidence 0.5, kind 'blog'). This record captures the full text read 2026-10-05. It exists because the accelerator record built from it contains the SAME class of false friend as cerebras-wse-3 and groq-lpu, and the trap is only visible in the white paper's own numbers. THE TWO TIERS, VERBATIM: 'd-Matrix Corsair is the world's densest integrated compute and memory solution packing 3200 mm2 of silicon in a single PCIe card, including 2 GB on-chip integrated Performance Memory at 150 TB/s memory bandwidth, and up to 256 GB off-chip Capacity Memory, with peak dense compute of 2400 TFLOPs for MXINT8 and 9600 TFLOPs for MXINT4 equivalent formats.' Dual card: '6400 mm2 silicon with 250B+ transistors, 16 chiplets with all-to-all connectivity, 19.2 PFLOPs of MXINT4 and 4 GB Performance Memory at 300 TB/s bandwidth, and up to 512 GB Capacity Memory.' THE FIGURE THAT PROVES THE TIERS ARE DIFFERENT MEMORIES AND THE POINT OF THIS SOURCE RECORD: Table 2, the 8-card inference server, gives 'Performance Memory 16 GB, 1200 TB/s' and 'Capacity Memory Up to 2 TB, 3.2 TB/s' and 'DMX Bridge bandwidth 2 TB/s'. So the vendor itself separates a 150 TB/s on-chip tier from a ~400 GB/s per-card off-chip tier (3.2 TB/s / 8 cards). THE 150 TB/s IS NOT THE PART'S MEMORY BANDWIDTH IN THE SENSE EVERY GPU FIELD MEANS IT, and 2 GB is not the part's memory capacity - it is only the tier that holds what is being worked on. A reader computing a roofline from 150000 GB/s for this card would conclude it has no memory bottleneck at all, which is false: a model larger than 2 GB has to cross LPDDR5. NUMERICS TABLE 1, VERBATIM: MXINT4 9600, MXINT8 2400, MXINT16 600 TFLOPs, with the footnote '*Both weights and activations in same format. TOPS can be higher with mixed precision. For example, MXINT4 weights and MXINT8 activations can provide 4800 TOPS.' So the repo's two existing rows (int8 2400, int4 9600) are correct and a third (int16 600) exists and was missing. OFF-CHIP TIER TECHNOLOGY, VERBATIM: 'The off-chip LPDDR5 Capacity Memory enables GenAI workloads in offline batched inference use cases.' 'Each chiplet has a standard PCIe5 x 16 interface for scale-out communication and two LPDDR interfaces, in addition to the DMX Link interfaces'. Scale-up: 'DMX Bridge' over 'four additional PCIe Gen5 x16 links', 'a pair of cards ... all-to-all topology across four packages (i.e., 16 chiplets)', and 8 cards per reference server over PCIe switches. ARCHITECTURE, VERBATIM: 'integrating a multiplier directly into memory bit cell using a logic process'; 'Digital IMC addresses the challenges of analog IMC, providing noise-free computation'; each chiplet 'consists of four Quads, each containing four Slices, a RISC-V control core, and a Dispatch Engine. Each Slice contains DIMC cores, SIMD cores, and a Data Reshape Engine'; 'proprietary network-on-chip' within a chiplet; 'DMX Link, a custom die-to-die interconnect based on OCP Open Domain-Specific Architecture (ODSA)'. WHAT IS NOT PUBLISHED: per-card Capacity Memory BANDWIDTH (only the 8-card server figure), Capacity Memory bus width, Capacity Memory capacity as a firm per-card number (the white paper says 'up to 256 GB'), TDP at the card level, and process node. The 19.2 PFLOPs dual-card and 76.8/19.2 PFLOPs 8-card server numbers are aggregates and must not be filed as per-card.