AWS Neuron documentation - Trainium2 Architecture page, including its per-chip Trainium (gen 1) comparison column

FIRST-PARTY HARDWARE DOCUMENTATION, and the closest thing AWS publishes to a datasheet for the Trainium line. Read in full 2026-10-05. Trainium2 per-chip figures, VERBATIM from the component table: 'Eight NeuronCore-v3 that collectively deliver: 1,299 FP8 TFLOPS; 667 BF16/FP16/TF32 TFLOPS; 2,563 FP8/FP16/BF16/TF32 sparse TFLOPS; 181 FP32 TFLOPS'. 'Device Memory: 96 GiB of device memory with 2.9 TB/sec of bandwidth.' 'Data Movement: 3.5 TB/sec of DMA bandwidth, with inline memory compression and decompression.' 'NeuronLink: NeuronLink-v3 for chip-to-chip interconnect provides 1.28 TB/sec bandwidth per chip.' 'Collective communication: 16 CC-Cores'. WHY THIS SOURCE MATTERS FOR THE GEN-1 PART, which is the reason it was fetched: AWS publishes NO Trainium (gen 1) datasheet, but this page's own comparison tables carry a per-chip Trainium column. VERBATIM, Compute table 'Trainium | Trainium2 | Improvement factor': FP8 (TFLOPS) 191 | 1299 | 6.7x; BF16/FP16/TF32 (TFLOPS) 191 | 667 | 3.4x; FP32 (TFLOPS) 48 | 181 | 3.7x; FP8/FP16/BF16/TF32 Sparse (TFLOPS) Not applicable | 2563 | Not applicable. Memory table: HBM Capacity (GiB) 32 | 96 | 3x; HBM Bandwidth (TB/sec) 0.8 | 2.9 | 3.6x; SBUF Capacity (MiB) 48 | 224 | 4.7x; Memory Pool Size Up to 16 chips | Up to 64 chips | 4x. Interconnect table: Inter-chip Interconnect (GB/sec/chip) 384 | 1280 | 3.3x. Data movement table: CC Cores 6 | 16 | 3.3x; SBUF memory layout Row-major | Row-major, Col-major-2B, Col-major-4B. THE FIGURES THAT MATTER MOST FOR THE RECORD ADDED IN THIS PASS, and the trap in them: the 191 TFLOPS figure is printed ONCE in a row labelled 'BF16/FP16/TF32', so it is one quantity covering three precisions, NOT three separate rows of the same number. The repo's aws-trainium3 record already makes this mistake-adjacent distinction correctly for Trn3 ('671 BF16/FP16/TF32 TFLOPS'); the same treatment is applied here. The 0.8 TB/s is the FIRST-PARTY per-chip memory bandwidth for gen-1 Trainium and it CONTRADICTS the 612.5 GB/s obtained by dividing the Trn1.32xlarge instance aggregate (9.8 TB/s / 16) - see w7z-aws-trn1-instance-page. Both are kept; the instance aggregate is the lower figure because it is an average the 16-chip instance sustains, not the chip's peak. 'Memory Pool Size Up to 16 chips' is also the Neuron memory-pooling mechanism, i.e. the chips in one instance can pool their HBM, which is a capability statement and not a capacity figure for a single chip. NEGATIVE FINDINGS: this page publishes no process node for any Trainium generation, no memory-bus width, no TDP, and no per-chip compute figure beyond the four rows above. It also names 'SBUF' - the on-chip scratch buffer - as a distinct memory tier, which is why the Trainium records must NOT treat SBUF as part of vram_gb.