inference/research
verifiedmedium · 0.80updated 2026-10-03

AMD Radeon Instinct MI60

amd GCN5.1 (gfx906, Vega20) 2018

Fields

id
accelerators/amd-radeon-instinct-mi60
Vendor
amd
Architecture
GCN5.1 (gfx906, Vega20)
Release year
2018
Process (nm)
7
Form factors
pcie
VRAM (GB)
32
Memory type
hbm2
Memory bus (bit)
4,096
Memory bandwidth (GB/s)
1,024
Bandwidth basis
AMD's spec table: 'Memory Interface 4096-bit, Memory Clock 1 GHz, Memory Bandwidth 1024 GB/s'. Same GCN5.1 memory subsystem as the MI50 and Radeon Pro VII - 4096-bit at 2.0 Gbps effective. The MI60 page states it flatly as 1024 GB/s rather than the MI50 datasheet's 'up to 1 TB/s'.
Peak FLOPS
precisionfp32tflops14.7denseyesvendor_claimyessource_idamd-mi60-product-pagebasisvendor-spec-sheetbasis_detailTranscribed from the vendor's own fp32 for AMD Radeon Instinct MI60 (source of record: 'AMD Radeon Instinct MI60 product page (archived 2018-11-22)', kind: spec-sheet). Recorded dense:true as printed.precisionfp16tflops29.5denseyesvendor_claimyessource_idamd-mi60-product-pagebasisvendor-spec-sheetbasis_detailTranscribed from the vendor's own fp16 for AMD Radeon Instinct MI60 (source of record: 'AMD Radeon Instinct MI60 product page (archived 2018-11-22)', kind: spec-sheet). Recorded dense:true as printed.precisionint8tflops58.9denseyesvendor_claimyessource_idamd-mi60-product-pagebasisvendor-spec-sheetbasis_detailTranscribed from the vendor's own int8 for AMD Radeon Instinct MI60 (source of record: 'AMD Radeon Instinct MI60 product page (archived 2018-11-22)', kind: spec-sheet). Recorded dense:true as printed.
TDP (W)
300
Unified memory
no
Consumer part
no
notes
AUDIT 2026-10-03 (AMD convention check, and the INT8 direction caveat): AMD's convention - 'Peak X Performance' = dense, 'Peak X Performance with Structured Sparsity' = sparse at exactly 2x - is established across six Instinct pages (source acc2-amd-ml300-convention). The MI60 page prints no structured-sparsity row for any precision, so all three rows are correctly dense:true. THE INT8 CAVEAT IS THE THING TO CARRY FORWARD FROM THIS RECORD: it stores int8 58.9 against fp16 29.5, i.e. INT8 at 2x FP16, exactly the Vega20/MI50X relationship. AMD's next part, the CDNA1 MI100, prints INT8 92.3 against FP16 184.6 - INT8 at HALF of FP16. So the Vega-generation MI50/MI60/Pro VII trio in this repo all show INT8 as a 2x-FP16 win, and every CDNA part shows it as a 1:2 loss. An int8 quantised model is therefore a win on Vega and a LOSS on CDNA relative to bf16, in per-flop terms, and this repo's quantization records should not be read as implying a uniform AMD INT8 advantage. The fastest GCN5.1 Instinct card, and the only source for its figures is an archived AMD page (2018-11-22) - the live URL 404s. 64 CUs / 4,096 SPs, 1800 MHz peak engine clock, up to 29.5 TFLOPS FP16, 14.7 TFLOPS FP32, 7.4 TFLOPS FP64, up to 58.9 TOPS INT8, 32 GB HBM2 ECC, 4096-bit, 1024 GB/s, 300W, passively cooled, full height / 267mm / double slot, PCIe 4.0 x16 plus PCIe 3.0 x16. AMD markets it as 'The World's First PCIe Gen 4 x16 Capable GPU' and, at the time, 'the world's fastest double precision PCIe accelerator' - the FP64 story (7.4 TFLOPS, GCN5's 1:2 FP64:FP32 ratio) was its actual differentiator against NVIDIA in 2018, not AI throughput. MI60 vs MI50X: the MI60 has 64 CUs / 4096 SPs / 1800 MHz versus the MI50's 60 / 3840 / (lower), giving 29.5 vs 26.5 TFLOPS FP16 and 58.9 vs 53.6 TOPS INT8. Same 32 GB HBM2 and same 1024 GB/s. So the MI60 is a compute bump on an identical memory configuration - the flops go up 11%, the bandwidth does not move at all. INT8 at 58.9 TOPS is 2x FP16, the GCN5 signature noted on the MI50X record too. Scale-up: 2 Infinity Fabric Links at 100 GB/s peak (AMD's page says 'up to 200 GB/s peer-to-peer' for the pair, i.e. 100 GB/s per link), supporting 'up to 2 GPU hives of 4 MI60 GPUs in a single server at up to 6x the speed of PCIe 3.0'. Far less scale-up bandwidth than any CDNA part. NOT ROCm-SUPPORTED TODAY: gfx906 is listed Unsupported in AMD's current ROCm system-requirements table (MI50/MI25/Radeon Pro VII/Radeon VII all share gfx906). Community-enabled only via ROCm/TheRock nightly builds, which AMD says are not part of the official release. Historical note on branding: MI60 is one of the last Instinct parts carrying the 'Radeon' brand. AMD dropped it at MI100 in November 2020. It is also one of the last Instinct cards able to output display - the MI50/MI60 generation kept display output, which the CDNA parts dropped.

Notes

AUDIT 2026-10-03 (AMD convention check, and the INT8 direction caveat): AMD's convention - 'Peak X Performance' = dense, 'Peak X Performance with Structured Sparsity' = sparse at exactly 2x - is established across six Instinct pages (source acc2-amd-ml300-convention). The MI60 page prints no structured-sparsity row for any precision, so all three rows are correctly dense:true. THE INT8 CAVEAT IS THE THING TO CARRY FORWARD FROM THIS RECORD: it stores int8 58.9 against fp16 29.5, i.e. INT8 at 2x FP16, exactly the Vega20/MI50X relationship. AMD's next part, the CDNA1 MI100, prints INT8 92.3 against FP16 184.6 - INT8 at HALF of FP16. So the Vega-generation MI50/MI60/Pro VII trio in this repo all show INT8 as a 2x-FP16 win, and every CDNA part shows it as a 1:2 loss. An int8 quantised model is therefore a win on Vega and a LOSS on CDNA relative to bf16, in per-flop terms, and this repo's quantization records should not be read as implying a uniform AMD INT8 advantage. The fastest GCN5.1 Instinct card, and the only source for its figures is an archived AMD page (2018-11-22) - the live URL 404s. 64 CUs / 4,096 SPs, 1800 MHz peak engine clock, up to 29.5 TFLOPS FP16, 14.7 TFLOPS FP32, 7.4 TFLOPS FP64, up to 58.9 TOPS INT8, 32 GB HBM2 ECC, 4096-bit, 1024 GB/s, 300W, passively cooled, full height / 267mm / double slot, PCIe 4.0 x16 plus PCIe 3.0 x16.

AMD markets it as 'The World's First PCIe Gen 4 x16 Capable GPU' and, at the time, 'the world's fastest double precision PCIe accelerator' - the FP64 story (7.4 TFLOPS, GCN5's 1:2 FP64:FP32 ratio) was its actual differentiator against NVIDIA in 2018, not AI throughput.

MI60 vs MI50X: the MI60 has 64 CUs / 4096 SPs / 1800 MHz versus the MI50's 60 / 3840 / (lower), giving 29.5 vs 26.5 TFLOPS FP16 and 58.9 vs 53.6 TOPS INT8. Same 32 GB HBM2 and same 1024 GB/s. So the MI60 is a compute bump on an identical memory configuration - the flops go up 11%, the bandwidth does not move at all.

INT8 at 58.9 TOPS is 2x FP16, the GCN5 signature noted on the MI50X record too.

Scale-up: 2 Infinity Fabric Links at 100 GB/s peak (AMD's page says 'up to 200 GB/s peer-to-peer' for the pair, i.e. 100 GB/s per link), supporting 'up to 2 GPU hives of 4 MI60 GPUs in a single server at up to 6x the speed of PCIe 3.0'. Far less scale-up bandwidth than any CDNA part.

NOT ROCm-SUPPORTED TODAY: gfx906 is listed Unsupported in AMD's current ROCm system-requirements table (MI50/MI25/Radeon Pro VII/Radeon VII all share gfx906). Community-enabled only via ROCm/TheRock nightly builds, which AMD says are not part of the official release.

Historical note on branding: MI60 is one of the last Instinct parts carrying the 'Radeon' brand. AMD dropped it at MI100 in November 2020. It is also one of the last Instinct cards able to output display - the MI50/MI60 generation kept display output, which the CDNA parts dropped.

Cross-references

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