inference/research
verifiedhigh · 0.92updated 2026-10-05

PCI Express 4.0

31.5 GB/s

Fields

id
interconnect/pcie-gen4
Kind
pcie
Version
4.0 (16 GT/s)
Bandwidth (GB/s, per link, unidirectional)
31.5
Bandwidth basis
x16, PER DIRECTION, and the value is UNCHANGED in this audit - it was already right and two earlier passes 'corrected' it in the wrong direction. CONVENTION ESTABLISHED AGAINST PCI-SIG'S OWN FAQ, which settles the ambiguity that has corrupted this record three times: PCIe figures are quoted PER LANE PER DIRECTION. PCI-SIG's PCIe 5.0 FAQ states PCIe 5.0 'adds support for 32.0 Gigabits/second/Lane/DIRECTION of raw bandwidth' and that 'a PCIe 5.0 Link consisting of 32 Lanes and operating at a bit rate of 32.0 GT/s provides an effective raw bandwidth of 128.0 Gigabytes/second IN EACH DIRECTION SIMULTANEOUSLY' - and 32 lanes x 32 Gb/s / 8 = 128.0 GB/s checks out, confirming the figure is per-direction and NOT an aggregate across both directions. PCIe is dual-simplex: the TX and RX lane pairs are independent, so a figure quoted 'in each direction' is already the per-direction payload and must NOT be halved again. THE ERROR THIS RECORD HAS SUFFERED TWICE, recorded because it is the most repeated mistake in this file: each direction IS the unit for a PCIe lane count, so 16 GT/s x 128/130 / 8 x 16 lanes = 31.5 GB/s per direction with no further halving. Halving it a second time to 15.75 produces a value that breaks the strict x2-per-generation ladder against pcie-gen5. Arithmetic from the 16 GT/s line rate and the 128b/130b coding PCIe 4.0 mandates: 16 x 128/130 / 8 = 1.969 GB/s per lane per direction, x16 = 31.51 GB/s per direction; the bidirectional aggregate is 63.02 GB/s. The earlier halving to 15.75 was wrong because it mistook the per-direction figure for an aggregate - and the pass before that had compounded the same error in the opposite direction by halving PCI-SIG's per-direction figure while claiming it was not an aggregate. Generational relationship now clean: 31.5 / 63.0 / 236 per direction for gens 4 / 5 / 6 (see pcie-gen4, pcie-gen5, pcie-gen6).
Link count
16
Topology
Point-to-point host-to-device (root complex to endpoint), up to 16 lanes. Becomes a shared fabric only via PCIe switches or host bridges.
Scale-up
yes
Scale-out
no
Switching
Optional PCIe switch, store-and-forward, no in-network reduction - collectives pay full hop latency per traversal.
notes
This is the generation that carried the first wave of PCIe-hosted multi-GPU inference boxes (MI100/MI210/MI250/MI250X-era parts). Inference consequence: 31.5 GB/s per direction at x16 is roughly 14x below NVLink 4's 450 GB/s per direction per GPU, so tensor parallel over PCIe 4.0 x16 costs dramatically more per layer boundary than the same sharding over NVLink, because activations must cross the host link while HBM bandwidth sits idle. Real deployments compensated by keeping tensor-parallel groups inside a single device and using pipeline parallelism across PCIe. WHY THE NEXT GENERATION IS NOT A CLEAN 2x ON PAYLOAD, because a reader will check: PCIe 5.0 doubles the GT/s rate (16 -> 32) and doubles the raw per-direction figure (32 -> 64 GB/s), and the payload per direction does follow exactly 2x here (31.5 -> 63.0), because Gen5 keeps the same NRZ 128b/130b coding as Gen4. The non-linearity starts one generation later - PCIe 6.0 goes to PAM4 with 242B/256B flit framing, and the payload per direction then rises only 1.92x (63.0 -> 121.0) even though the GT/s rate doubles again. See pcie-gen6 and pcie-gen7 for that step and the reason for it. DIRECTION AUDIT TRAIL, kept because this record is the cautionary case in the repo: it has been through three values (15.75, 31.5, and a halved-then-re-halved 31.5 with prose asserting 15.75) across three audit passes, all from the same underlying ambiguity. The resolution is that PCI-SIG quotes PCIe bandwidth per lane per direction, so the ladder is 4.0 / 8.0 / 15.75 / 31.5 / 63.0 / 121.0 / 242.0 per direction at x16 for gens 1 through 7 and must never be halved again. Any comparison against an NVLink, Infinity Fabric or CXL number in this repo must first check that record's convention - nvlink-4 and nvswitch-4 store HALVED per-direction values because NVIDIA publishes bidirectional aggregates, which is the opposite convention from PCI-SIG's, and that asymmetry is real and is the root of the error.
way
each

Notes

This is the generation that carried the first wave of PCIe-hosted multi-GPU inference boxes (MI100/MI210/MI250/MI250X-era parts). Inference consequence: 31.5 GB/s per direction at x16 is roughly 14x below NVLink 4's 450 GB/s per direction per GPU, so tensor parallel over PCIe 4.0 x16 costs dramatically more per layer boundary than the same sharding over NVLink, because activations must cross the host link while HBM bandwidth sits idle. Real deployments compensated by keeping tensor-parallel groups inside a single device and using pipeline parallelism across PCIe. WHY THE NEXT GENERATION IS NOT A CLEAN 2x ON PAYLOAD, because a reader will check: PCIe 5.0 doubles the GT/s rate (16 -> 32) and doubles the raw per-direction figure (32 -> 64 GB/s), and the payload per direction does follow exactly 2x here (31.5 -> 63.0), because Gen5 keeps the same NRZ 128b/130b coding as Gen4. The non-linearity starts one generation later - PCIe 6.0 goes to PAM4 with 242B/256B flit framing, and the payload per direction then rises only 1.92x (63.0 -> 121.0) even though the GT/s rate doubles again. See pcie-gen6 and pcie-gen7 for that step and the reason for it. DIRECTION AUDIT TRAIL, kept because this record is the cautionary case in the repo: it has been through three values (15.75, 31.5, and a halved-then-re-halved 31.5 with prose asserting 15.75) across three audit passes, all from the same underlying ambiguity. The resolution is that PCI-SIG quotes PCIe bandwidth per lane per direction, so the ladder is 4.0 / 8.0 / 15.75 / 31.5 / 63.0 / 121.0 / 242.0 per direction at x16 for gens 1 through 7 and must never be halved again. Any comparison against an NVLink, Infinity Fabric or CXL number in this repo must first check that record's convention - nvlink-4 and nvswitch-4 store HALVED per-direction values because NVIDIA publishes bidirectional aggregates, which is the opposite convention from PCI-SIG's, and that asymmetry is real and is the root of the error.

Cross-references

This record references no other records — it is a leaf. It is cited by 1332.