inference/research
verifiedhigh · 0.90updated 2026-10-05

AMD Radeon Pro VII

amd GCN5.1 (gfx906, Vega20) 2019

Fields

id
accelerators/amd-radeon-pro-vii
Vendor
amd
Architecture
GCN5.1 (gfx906, Vega20)
Release year
2019
Process (nm)
7
Form factors
pcie
VRAM (GB)
16
Memory type
hbm2
Memory bus (bit)
4,096
Memory bandwidth (GB/s)
1,024
Bandwidth basis
AMD's spec table says 'Memory Bandwidth: Up to 1024 GB/s' on a 4096-bit interface with no memory-clock figure given. 1024 GB/s at 4096 bits implies a 2.0 Gbps effective per-pin rate. The page's own prose is looser ('running over a 1 TB per second memory bus'). Use 1024 GB/s as AMD's ceiling figure; it is a maximum, not a measured or typical figure, and there is no published clock to re-derive it from.
Peak FLOPS
precisionfp32tflops13.1denseyesvendor_claimyessource_idamd-radeon-pro-vii-product-pagebasisvendor-spec-sheetbasis_detailTranscribed from the vendor's own fp32 for AMD Radeon Pro VII (source of record: 'AMD Radeon Pro VII product page (archived 2021-02-16)', kind: spec-sheet). Recorded dense:true as printed.precisionfp64tflops6.5denseyesvendor_claimyessource_idamd-radeon-pro-vii-product-pagebasisvendor-spec-sheetbasis_detailADDED 2026-10-05. Vendor spec table, verbatim: 'Peak Double Precision (FP64) Performance 6.5 TFLOPs', immediately below 'Peak Single Precision (FP32) Performance 13.1 TFLOPs'. This record's own notes previously said of this figure 'The vector FP64 rate is not listed on this page ... the page's memory of Peak Double Precision (FP64) 6.5 TFLOPs does appear in the archived page - that figure is AMD-stated but is not in the flops list because the schema enum has no fp64.' Both halves of that sentence were true of an older state: the schema NOW HAS an 'fp64' member (added 2026-10-04 to stop FP64 rows being parked in 'other'), and the page does list it. So the row was omitted for a reason that has since been removed and is added here. The GCN5 1:2 FP64:FP32 ratio predicts 13.1/2 = 6.55, which is consistent with AMD's 6.5 to the rounding AMD uses, so the figure is internally coherent. Dense as printed: the page carries no sparsity footnote at all (verified - 'sparsit' and 'Structured Sparsity' return zero matches over the full 22,831-character extract). Do not halve it.
TDP (W)
250
Unified memory
no
Consumer part
no
notes
AUDIT CORRECTION 2026-10-05: A PRIOR NEGATIVE FINDING ABOUT THIS RECORD WAS WRONG, AND IT IS THE BEST EXAMPLE OF THE FAILURE MODE IN THIS REPO. w4h-amd-radeon-pro-vii-product-page-dense concluded, from reading this very page: 'the rendered page as extracted contains NO TFLOPS figure, NO "Peak ... Performance" specification row, and no sparsity footnote. A regex sweep for "sparsit", "TFLOPS", "TFLOP", "TOPS" and "Peak " over the full extracted text of 18,346 characters returned ZERO matches.' That is false. The page carries a complete GPU Specifications table, and re-reading it returns: 'Peak Single Precision (FP32) Performance 13.1 TFLOPs', 'Peak Double Precision (FP64) Performance 6.5 TFLOPs', 'GPU Memory 16 GB', 'Memory Type (GPU) HBM2', 'Memory Interface 4096-bit', 'Memory Bandwidth Up to 1024 GB/s', 'Memory ECC Support Yes', 'Stream Processors 3840', 'Compute Units 60', 'Lithography TSMC 7nm FinFET', 'TBP 250W', 'Bus Type PCIe 4.0 x16'. The earlier pass's own conclusion was self-undermining and it said so: it noted the stored 13.1 was 'widely attributed to AMD' and 'should be treated as unestablished' - while attributing it to the page it had just declared to contain no compute figure at all. A probe that reports zero matches for the exact words 'Peak ' and 'TFLOPs' is not evidence of absence; it is evidence that the probe failed. Four independent methods now confirm the figures are present: (1) plain web_extract of the archived URL, full spec table located; (2) a keyword sweep over that extract returning 2 hits for 'TFLOPs', 2 for 'Peak', 0 for 'sparsit'; (3) direct regex on each stored value, giving 1 occurrence each of '13.1', '1024' and '4096'; and (4) reading the surrounding table text, which is quoted above. The sparsity question the negative was opened to answer is ALSO now settled: the page carries NO sparsity footnote and no row titled for structured sparsity ('sparsit' and 'Structured Sparsity' both return zero matches), so AMD's convention on this pre-Instinct page is that the single printed figure is dense. dense:true is correct and must not be halved. SO TWO CORRECTIONS LAND HERE: the fp32 13.1 row is confirmed as genuinely vendor-stated (it already was, and the citation now has a source record that actually quotes the table), and an fp64 6.5 row is ADDED - the notes had wrongly recorded it as unavailable 'because the schema enum has no fp64', a constraint removed on 2026-10-04 when 'fp64' was added to the enum precisely so FP64 rows would stop being parked in 'other'. MEMORY, CONFIRMED AGAINST THE SAME TABLE: 'Memory Interface 4096-bit' and 'Memory Bandwidth Up to 1024 GB/s' both appear, so the stored 4096 and 1024 are first-party. 1024 GB/s at 4096 bits implies a 2.0 Gbps effective per-pin rate, and AMD publishes no memory clock to re-derive it from, so that remains an inference - though a well-constrained one, since it follows from two printed numbers. Everything else in this record stands, including the caveat that dominates its usefulness: THIS CARD IS NOT ROCm-SUPPORTED. AMD's current ROCm requirements list 'AMD Radeon PRO VII | GCN5.1 | gfx906 | Unsupported'. So the 16 GB of HBM2 at ~1 TB/s is not reachable by any shipping engine. For LLM inference this card is bandwidth-starved regardless: a 7B model at fp16 does not fit in 16 GB, and at 4-bit barely does, leaving almost nothing for KV cache. Two features later Instinct parts dropped: display outputs (6x, FrameLock/GenLock for broadcast) and an Infinity Fabric Link 2 bridge connector for peer-to-peer GPU-to-GPU memory pooling between two cards - AMD describes it as forming 'a combined pool of GPU memory', and for a two-card workstation that is the only scale-up story here. ARCHITECTURE NAMING: gfx906 is shared with Radeon VII and Instinct MI50/MI50X. Do not assume a card reporting gfx906 is this SKU. Source caveat: the live AMD product URL 404s today, so all figures come from the 2021-02-16 Wayback capture.

Notes

AUDIT CORRECTION 2026-10-05: A PRIOR NEGATIVE FINDING ABOUT THIS RECORD WAS WRONG, AND IT IS THE BEST EXAMPLE OF THE FAILURE MODE IN THIS REPO. w4h-amd-radeon-pro-vii-product-page-dense concluded, from reading this very page: 'the rendered page as extracted contains NO TFLOPS figure, NO "Peak ... Performance" specification row, and no sparsity footnote. A regex sweep for "sparsit", "TFLOPS", "TFLOP", "TOPS" and "Peak " over the full extracted text of 18,346 characters returned ZERO matches.' That is false. The page carries a complete GPU Specifications table, and re-reading it returns: 'Peak Single Precision (FP32) Performance 13.1 TFLOPs', 'Peak Double Precision (FP64) Performance 6.5 TFLOPs', 'GPU Memory 16 GB', 'Memory Type (GPU) HBM2', 'Memory Interface 4096-bit', 'Memory Bandwidth Up to 1024 GB/s', 'Memory ECC Support Yes', 'Stream Processors 3840', 'Compute Units 60', 'Lithography TSMC 7nm FinFET', 'TBP 250W', 'Bus Type PCIe 4.0 x16'. The earlier pass's own conclusion was self-undermining and it said so: it noted the stored 13.1 was 'widely attributed to AMD' and 'should be treated as unestablished' - while attributing it to the page it had just declared to contain no compute figure at all. A probe that reports zero matches for the exact words 'Peak ' and 'TFLOPs' is not evidence of absence; it is evidence that the probe failed. Four independent methods now confirm the figures are present: (1) plain web_extract of the archived URL, full spec table located; (2) a keyword sweep over that extract returning 2 hits for 'TFLOPs', 2 for 'Peak', 0 for 'sparsit'; (3) direct regex on each stored value, giving 1 occurrence each of '13.1', '1024' and '4096'; and (4) reading the surrounding table text, which is quoted above. The sparsity question the negative was opened to answer is ALSO now settled: the page carries NO sparsity footnote and no row titled for structured sparsity ('sparsit' and 'Structured Sparsity' both return zero matches), so AMD's convention on this pre-Instinct page is that the single printed figure is dense. dense:true is correct and must not be halved. SO TWO CORRECTIONS LAND HERE: the fp32 13.1 row is confirmed as genuinely vendor-stated (it already was, and the citation now has a source record that actually quotes the table), and an fp64 6.5 row is ADDED - the notes had wrongly recorded it as unavailable 'because the schema enum has no fp64', a constraint removed on 2026-10-04 when 'fp64' was added to the enum precisely so FP64 rows would stop being parked in 'other'. MEMORY, CONFIRMED AGAINST THE SAME TABLE: 'Memory Interface 4096-bit' and 'Memory Bandwidth Up to 1024 GB/s' both appear, so the stored 4096 and 1024 are first-party. 1024 GB/s at 4096 bits implies a 2.0 Gbps effective per-pin rate, and AMD publishes no memory clock to re-derive it from, so that remains an inference - though a well-constrained one, since it follows from two printed numbers. Everything else in this record stands, including the caveat that dominates its usefulness: THIS CARD IS NOT ROCm-SUPPORTED. AMD's current ROCm requirements list 'AMD Radeon PRO VII | GCN5.1 | gfx906 | Unsupported'. So the 16 GB of HBM2 at ~1 TB/s is not reachable by any shipping engine. For LLM inference this card is bandwidth-starved regardless: a 7B model at fp16 does not fit in 16 GB, and at 4-bit barely does, leaving almost nothing for KV cache. Two features later Instinct parts dropped: display outputs (6x, FrameLock/GenLock for broadcast) and an Infinity Fabric Link 2 bridge connector for peer-to-peer GPU-to-GPU memory pooling between two cards - AMD describes it as forming 'a combined pool of GPU memory', and for a two-card workstation that is the only scale-up story here. ARCHITECTURE NAMING: gfx906 is shared with Radeon VII and Instinct MI50/MI50X. Do not assume a card reporting gfx906 is this SKU. Source caveat: the live AMD product URL 404s today, so all figures come from the 2021-02-16 Wayback capture.

Cross-references

Interconnect (2)