AMD Radeon PRO W7900

ADDED 2026-10-03 to close a real gap: this id was referenced by gotcha-aiter-gate-skips-rdna3-gfx1100 (and sits in that gotcha's affects[] array) with no accelerator record anywhere in the repo. Built from AMD's own two-page datasheet (source acc2-amd-radeon-pro-w7900-datasheet), not from the product page - AMD's current W7900 product page returns HTTP 404, while the datasheet PDF is still served and was archived 2024-06-03, so the datasheet is the durable primary source. WHY THIS PART MATTERS FOR LLM INFERENCE, and why the sparse compute spec is not the limiting factor: the datasheet's headline is 48 GB of ECC'd GDDR6 on a 384-bit interface at 864 GB/s, and the key-features list adds '2x AI Accelerators per Compute Unit' (i.e. the second-gen Matrix/AI accelerator per CU that RDNA 3 introduced). 48 GB of ECC'd GDDR6 with ECC enabled is unusual and is the whole story for on-prem serving: it is the largest ECC memory pool available on a PCIe workstation card short of the Instinct line, which matters because a 32 GB consumer card has nowhere to go once you have weights plus KV plus activations. That makes the W7900 the natural 'quiet workstation, ECC, 48 GB' part for a 30-70B model at 4-8 bit, even though its published compute figure is only 61.32 TFLOPS FP32. THE CAVEAT THAT DOMINATES ANY USE OF THIS CARD, and the reason its absence from the repo until now was a real defect: it is RDNA 3 / gfx1100, and vLLM's AITER gate silently excludes it. vLLM's is_aiter_found_and_supported() requires get_cdna_version() > 2 (CDNA3 or newer) and the separate RDNA path is gated on gfx1201 only, so gfx1100 falls into neither branch and vLLM logs 'AITER is not found or not supported on the current platform, QuarkOCP_MX will fall back to emulation' and selects TritonInt8ScaledMMLinearKernel instead of AiterInt8ScaledMMLinearKernel - with no error raised. AITER upstream lists 'AMD Pro W7900 | gfx1100 (RDNA3) | Experimental', and the library's CK/ASM kernels are CDNA-only, so gfx1100 needs the Triton WMMA route regardless. A vLLM maintainer confirmed RDNA support is not on the vLLM roadmap (redirected to ROCm/aiter#4604), so treat W7900 as unsupported for AITER-accelerated formats unless the four-part patch in vllm#51136 is applied. This is the same defect the sibling record amd-radeon-rx-7900-xtx already carries, and it applies to both because they are the same die. RELATIONSHIP TO THE EXISTING SIBLING RECORD amd-radeon-rx-7900-xtx: same RDNA 3 family and the same gfx1100 software story, but different memory - 24 GB / 384-bit / 96 GB/s-class consumer configuration versus 48 GB / 384-bit / 864 GB/s with ECC here. The bandwidth gap is roughly an order of magnitude, which is what makes the professional card the one that can actually hold a working set. WHAT AMD DOES NOT PUBLISH, left null rather than derived: no FP16 matrix throughput, no INT8 throughput, no AI TOPS figure, no bus-level data rate, no process node on the datasheet itself (process_nm 5 is the RDNA 3 family's published node, consistent with AMD's other RDNA 3 records here, not a figure from this sheet), and no ECC capacity overhead. INTERCONNECT FILLED 2026-10-04: this record had NO interconnect key at all; it now reads ['pcie-gen4'], from the vendor's own spec table ('AMD's W7900 datasheet row 'PCI Express Support: 4.0 Ready (x16) with 3.0 Backward Compatibility''). Note the backward-compatibility clause is part of the vendor's published value and is why the field records the HIGHEST supported generation rather than the lane count: the interconnect schema has no lane-count or backward-compatibility field, so 'pcie-gen4' on a '4.0 Ready (x16) with 3.0 Backward Compatibility' card means 'Gen 4 is what this part supports at full rate', not 'Gen 3 cards cannot be used'. Scale-up fabric: none. This is a single-slot-scale workstation card with no Infinity Fabric link exposed to software and no multi-GPU interconnect of any kind in the datasheet.