Biren BILI 166 series (166C inference card / 166M / 166L OAM modules)

None available. Biren publishes no memory capacity, type, bus width or bandwidth for any BILI 166 part. This is the central documentation gap for this record and the reason its confidence is low. Biren claims first-in-China GPU-to-OCS optical interconnect commercialisation (source cn-biren-bili-166), which if accurate implies an unusually strong scale-out story, but no bandwidth figure accompanies the claim.

THE HIERARCHY POINT: Biren is the clearest case in this slice where a well-known company has essentially no public specification, and the honest record is a low-confidence draft that documents what is claimed and what is missing rather than a confident number. THREE DIFFERENT PRODUCTS, THREE TDPs, ZERO COMPUTE FIGURES. The vendor's own product pages (cn-biren-bili-166) publish form factor and power and nothing else: 166C is a full-height full-length 290 mm dual-width PCIe INFERENCE card at 300 W peak, explicitly positioned for high cost-performance and drop-in compatibility with existing 4-8U PCIe GPU servers, aimed at large-model, multimodal AIGC, image and speech recognition, NLP and recommendation workloads; 166M is a 4U OAM V1.1 AIR-COOLED train+infer module at 550 W peak; 166L is the same in COLD-PLATE LIQUID COOLING at 600 W peak. Not one of the three pages carries a TOPS figure, a TFLOPS figure, a memory capacity, a memory type or a bandwidth number. Consequently the flops array is empty, vram_gb and memory_bandwidth_gbps are None, and NO INFERENCE ROOFLINE CAN BE COMPUTED FOR THIS PART from any available source - which is exactly the information a memory-bound inference study needs and cannot get. What CAN be substantiated about the company: it was founded in 2019 by Lingjie Xu, Zhang Wen (ex-SenseTime president) and Jiao Guofang (ex-Huawei), has been on the BIS Entity List since October 2023, lost co-founder Xu Lingjie after the sanctions-related losses, raised substantial state-backed funding (RMB 1.5bn as of June 2025), and listed on HKEX as 6082 on 2 January 2026 with shares soaring on debut (cn-biren-wikipedia). The older BR100/BR104 parts have the famous 2022 launch claim of '77 billion transistors, 2 PFLOPS of AI performance' (Tom's Hardware) and 'comparable to H100' positioning - but those are 2022 PRESS-RELEASE figures for a part whose foundry, TSMC, HALTED all manufacturing in October 2022, and which Biren was subsequently reported to have modified to process less data specifically so it would fall below the US control threshold (FT, The Register). That means the BR100's 2 PFLOPS claim describes silicon that was never lawfully produced in volume, and it is a historical marketing claim rather than a shipping spec. Note the naming discontinuity: BR100/BR104 gave way to BILI (壁砺) 166, and DIGITIMES reported in October 2026 that Biren is preparing a next-generation BR20X around broader low-precision support and locally available manufacturing. THE PRACTICAL CONCLUSION: Biren is a real, listed, shipping vendor with inference SKUs aimed squarely at this repo's workload, and is simultaneously undocumented to the point where none of its parts can be placed on a roofline. That combination makes it the highest-value open question in the Chinese accelerator set. MEMORY_BUS_WIDTH: STILL NULL, AND HERE IS PRECISELY WHAT WAS LOOKED FOR (2026-10-04). The vendor publishes NO memory-bus width for this part, and none was back-computed from the published bandwidth. NO FIGURE WAS BACK-COMPUTED FROM BANDWIDTH.[REPAIRED 2026-10-08 by w8-reverify. This sentence previously read '(2026-10-04). %s NO FIGURE WAS BACK-COMPUTED FROM BANDWIDTH' — a literal printf placeholder left in the JSON by the wave-3 pass (commit 9968769) across 34 accelerator records, and invisible to every check in this repo because validate.py never reads notes. The substitution text is the same boilerplate the 7 uncorrupted records in this family already carry, and it is only valid here because memory_bus_bit is null on every one of the 34, so "the vendor does not publish it" is the true state. A record with a non-null memory_bus_bit must NOT receive this filler.] That is the standing rule for this field in this repo and it was applied to every null here rather than to a subset: a width derived by dividing a published aggregate bandwidth by an assumed or half-assumed per-pin rate is two inferences stacked on one number, and if either inference is wrong the record looks populated while being wrong. The correct state of this field is 'the vendor does not publish it', and the note above names the specific document that was read and found not to carry it, so a future pass does not have to re-establish that from scratch. MEMORY_BUS_WIDTH: STILL NULL, AND HERE IS PRECISELY WHAT WAS LOOKED FOR (2026-10-04). Biren publishes no memory bus width for the BR100, BR104 or BILI 166 parts. The Hot Chips BR100 presentation is a floorplan-level talk and states capacity and the two-die topology, not an interface width. NO FIGURE WAS BACK-COMPUTED FROM BANDWIDTH. That is the standing rule for this field in this repo and it was applied to every null here rather than to a subset: a width derived by dividing a published aggregate bandwidth by an assumed or half-assumed per-pin rate is two inferences stacked on one number, and if either is wrong the record looks populated while being wrong. The correct state of this field is 'the vendor does not publish it', and the text above names the specific document read and found not to carry it, so a future pass does not have to re-establish that from scratch.