inference/research
verifiedmedium · 0.75updated 2026-10-10

FuriosaAI Warboy

asic-other Warboy (Gen 1 Vision NPU) 2021

Fields

id
accelerators/furiosaai-warboy
Vendor
asic-other
Architecture
Warboy (Gen 1 Vision NPU)
Release year
2021
Process (nm)
14
Form factors
pcie
VRAM (GB)
16
Memory type
lpddr4x
Memory bandwidth (GB/s)
66
Bandwidth basis
Vendor-published: 66 GB/s DRAM bandwidth (FuriosaAI developer docs). LPDDR4x at 4266 MT/s.
Peak FLOPS
precisionint8tflops64denseyesvendor_claimyessource_idfuriosaai-warboy-developer-docsnotes64 TOPS INT8 dense. Peak performance figure from FuriosaAI developer documentation.basisvendor-docsbasis_detailfuriosaai Warboy developer docs.
TDP (W)
40
Unified memory
no
Consumer part
no
notes
REAL VENDOR: FuriosaAI (furiosa.ai, Seoul, South Korea). Set to 'asic-other' because the schema enum does not include 'furiosaai'. Warboy is FuriosaAI's Gen 1 Vision NPU, built on Samsung 14nm with 5 billion transistors on a 180mm^2 die at 2GHz clock. 64 TOPS INT8, 66 GB/s LPDDR4x, PCIe Gen4 8x. The chip is designed for vision AI workloads — object detection, segmentation, classification — at the edge and in the datacenter. FuriosaAI SDK compiles TFLite and ONNX models for the Warboy NPU. The company has shipped two silicon generations: Warboy (Samsung 14nm, 2021) and RNGD ('Renegade', TSMC 5nm, mass production January 2026). A third generation co-developed with Broadcom (2nm compute die, HBM4/4E) was announced in May 2026 but is not yet in production. Warboy is NOT an LLM serving chip — it is a vision NPU. The successor RNGD targets LLM inference with higher compute and HBM. Process node is Samsung 14nm (not TSMC). TDP is 40W for the PCIe card. MEMORY_BUS_WIDTH: STILL NULL, AND HERE IS PRECISELY WHAT WAS LOOKED FOR (2026-10-04). The vendor publishes NO memory-bus width for this part, and none was back-computed from the published bandwidth. NO FIGURE WAS BACK-COMPUTED FROM BANDWIDTH.[REPAIRED 2026-10-08 by w8-reverify. This sentence previously read '(2026-10-04). %s NO FIGURE WAS BACK-COMPUTED FROM BANDWIDTH' — a literal printf placeholder left in the JSON by the wave-3 pass (commit 9968769) across 34 accelerator records, and invisible to every check in this repo because validate.py never reads notes. The substitution text is the same boilerplate the 7 uncorrupted records in this family already carry, and it is only valid here because memory_bus_bit is null on every one of the 34, so "the vendor does not publish it" is the true state. A record with a non-null memory_bus_bit must NOT receive this filler.] That is the standing rule for this field in this repo and it was applied to every null here rather than to a subset: a width derived by dividing a published aggregate bandwidth by an assumed or half-assumed per-pin rate is two inferences stacked on one number, and if either inference is wrong the record looks populated while being wrong. The correct state of this field is 'the vendor does not publish it', and the note above names the specific document that was read and found not to carry it, so a future pass does not have to re-establish that from scratch. MEMORY_BUS_WIDTH: STILL NULL, AND HERE IS PRECISELY WHAT WAS LOOKED FOR (2026-10-04). FuriosaAI's own Warboy spec page publishes 'Memory Bandwidth 66GB/s' and 'LPDDR4X 16GB' with no bus width and no pin rate. Not back-computed: 66 GB/s divided by an assumed LPDDR4X rate would be a guess about the speed grade as well as the width. NO FIGURE WAS BACK-COMPUTED FROM BANDWIDTH. That is the standing rule for this field in this repo and it was applied to every null here rather than to a subset: a width derived by dividing a published aggregate bandwidth by an assumed or half-assumed per-pin rate is two inferences stacked on one number, and if either is wrong the record looks populated while being wrong. The correct state of this field is 'the vendor does not publish it', and the text above names the specific document read and found not to carry it, so a future pass does not have to re-establish that from scratch. VRAM_GB FILLED 2026-10-10: vram_gb null -> 16. The vendor's own specification page https://furiosa.ai/warboy/specs publishes 'Memory Capacity LPDDR4X 16GB' alongside 'Memory Bandwidth 66GB/s'.

Notes

REAL VENDOR: FuriosaAI (furiosa.ai, Seoul, South Korea). Set to 'asic-other' because the schema enum does not include 'furiosaai'. Warboy is FuriosaAI's Gen 1 Vision NPU, built on Samsung 14nm with 5 billion transistors on a 180mm^2 die at 2GHz clock. 64 TOPS INT8, 66 GB/s LPDDR4x, PCIe Gen4 8x. The chip is designed for vision AI workloads — object detection, segmentation, classification — at the edge and in the datacenter. FuriosaAI SDK compiles TFLite and ONNX models for the Warboy NPU. The company has shipped two silicon generations: Warboy (Samsung 14nm, 2021) and RNGD ('Renegade', TSMC 5nm, mass production January 2026). A third generation co-developed with Broadcom (2nm compute die, HBM4/4E) was announced in May 2026 but is not yet in production. Warboy is NOT an LLM serving chip — it is a vision NPU. The successor RNGD targets LLM inference with higher compute and HBM. Process node is Samsung 14nm (not TSMC). TDP is 40W for the PCIe card. MEMORY_BUS_WIDTH: STILL NULL, AND HERE IS PRECISELY WHAT WAS LOOKED FOR (2026-10-04). The vendor publishes NO memory-bus width for this part, and none was back-computed from the published bandwidth. NO FIGURE WAS BACK-COMPUTED FROM BANDWIDTH.[REPAIRED 2026-10-08 by w8-reverify. This sentence previously read '(2026-10-04). %s NO FIGURE WAS BACK-COMPUTED FROM BANDWIDTH' — a literal printf placeholder left in the JSON by the wave-3 pass (commit 9968769) across 34 accelerator records, and invisible to every check in this repo because validate.py never reads notes. The substitution text is the same boilerplate the 7 uncorrupted records in this family already carry, and it is only valid here because memory_bus_bit is null on every one of the 34, so "the vendor does not publish it" is the true state. A record with a non-null memory_bus_bit must NOT receive this filler.] That is the standing rule for this field in this repo and it was applied to every null here rather than to a subset: a width derived by dividing a published aggregate bandwidth by an assumed or half-assumed per-pin rate is two inferences stacked on one number, and if either inference is wrong the record looks populated while being wrong. The correct state of this field is 'the vendor does not publish it', and the note above names the specific document that was read and found not to carry it, so a future pass does not have to re-establish that from scratch.

MEMORY_BUS_WIDTH: STILL NULL, AND HERE IS PRECISELY WHAT WAS LOOKED FOR (2026-10-04). FuriosaAI's own Warboy spec page publishes 'Memory Bandwidth 66GB/s' and 'LPDDR4X 16GB' with no bus width and no pin rate. Not back-computed: 66 GB/s divided by an assumed LPDDR4X rate would be a guess about the speed grade as well as the width. NO FIGURE WAS BACK-COMPUTED FROM BANDWIDTH. That is the standing rule for this field in this repo and it was applied to every null here rather than to a subset: a width derived by dividing a published aggregate bandwidth by an assumed or half-assumed per-pin rate is two inferences stacked on one number, and if either is wrong the record looks populated while being wrong. The correct state of this field is 'the vendor does not publish it', and the text above names the specific document read and found not to carry it, so a future pass does not have to re-establish that from scratch.

VRAM_GB FILLED 2026-10-10: vram_gb null -> 16. The vendor's own specification page https://furiosa.ai/warboy/specs publishes 'Memory Capacity LPDDR4X 16GB' alongside 'Memory Bandwidth 66GB/s'.

Cross-references

Interconnect (1)