inference/research
verifiedhigh · 0.95updated 2026-10-03

Google Cloud TPU v6e (Trillium)

google v6e (Trillium) 2024

Fields

id
accelerators/google-tpu-v6e
Vendor
google
Architecture
v6e (Trillium)
Release year
2024
Process (nm)
7
Form factors
custom
VRAM (GB)
32
Memory type
hbm
Memory bandwidth (GB/s)
1,638
Bandwidth basis
Vendor-published per-chip HBM bandwidth of 1638 GBps; memory generation and bus width not stated in the spec table.
Peak FLOPS
precisionbf16tflops918denseyesvendor_claimyessource_idasic-tpu-v6e-specsbasisvendor-spec-sheetbasis_detailTranscribed from the vendor's own bf16 for Google Cloud TPU v6e (Trillium) (source of record: 'Cloud TPU v6e (Trillium) system architecture', kind: spec-sheet). Recorded dense:true as printed.precisionint8tflops1,836denseyesvendor_claimyessource_idasic-tpu-v6e-specsbasisvendor-spec-sheetbasis_detailTranscribed from the vendor's own int8 for Google Cloud TPU v6e (Trillium) (source of record: 'Cloud TPU v6e (Trillium) system architecture', kind: spec-sheet). Recorded dense:true as printed.
Unified memory
yes
Consumer part
no
notes
Per-chip figures. Google calls out 'Performance/total cost of ownership (expected) 1' as a published spec row, i.e. the headline claim is a ratio against v5e rather than a raw number. Unlike v5p, v6e does publish INT8 = 2x BF16 (1836 TOPS vs 918 TFLOPS), so v6e restored the int8-doubling that v4 did not have. 32 GB HBM at 1638 GB/s gives 560 FLOP/byte BF16, the highest compute-to-byte ratio of any Google part here, so v6e is the first TPU where larger batch prefill actually becomes compute-feasible rather than purely bandwidth-limited. Two MXUs per TensorCore (down from four on v4/v5p/v5e), which shifts the weight-stationary geometry rather than the totals. Pod = 256 chips on a 2D torus, ICI 800 GBps bidirectional per chip with 4 ports, plus SparseCore units for embedding-style irregular access. v6e-8 is a full-host 8-chip slice explicitly optimised for single-workload inference. MEMORY_BUS_WIDTH: STILL NULL, AND HERE IS PRECISELY WHAT WAS LOOKED FOR (2026-10-04). The vendor publishes no memory-bus width for this part, and none was back-computed from the published bandwidth. This is the correct state of the field for a part with no vendor width figure.

Notes

Per-chip figures. Google calls out 'Performance/total cost of ownership (expected) 1' as a published spec row, i.e. the headline claim is a ratio against v5e rather than a raw number. Unlike v5p, v6e does publish INT8 = 2x BF16 (1836 TOPS vs 918 TFLOPS), so v6e restored the int8-doubling that v4 did not have. 32 GB HBM at 1638 GB/s gives 560 FLOP/byte BF16, the highest compute-to-byte ratio of any Google part here, so v6e is the first TPU where larger batch prefill actually becomes compute-feasible rather than purely bandwidth-limited. Two MXUs per TensorCore (down from four on v4/v5p/v5e), which shifts the weight-stationary geometry rather than the totals. Pod = 256 chips on a 2D torus, ICI 800 GBps bidirectional per chip with 4 ports, plus SparseCore units for embedding-style irregular access. v6e-8 is a full-host 8-chip slice explicitly optimised for single-workload inference. MEMORY_BUS_WIDTH: STILL NULL, AND HERE IS PRECISELY WHAT WAS LOOKED FOR (2026-10-04). The vendor publishes no memory-bus width for this part, and none was back-computed from the published bandwidth. This is the correct state of the field for a part with no vendor width figure.

Cross-references

Interconnect (1)