Google TPU v6e: 918 BF16 TFLOPS per chip

Vendor-published per-chip specification. Single TensorCore with 2 MXUs (256x256 each). 32 GB HBM at 1638 GB/s. 256-chip pod on 2D torus with ICI 800 GB/s bidirectional per chip.

Vendor-published peak compute specification. The 918 TFLOPS is the theoretical BF16 peak per chip. No inference throughput (tokens/sec) is published by Google for TPU v6e. Google publishes no MFU or inference benchmark figures for TPU. The INT8 figure is 1836 TOPS (2x BF16). LOAD-CONDITION AUDIT (bq- 2026-10-04). SCENARIO: NOT STATED by the source - absent, not inferred. A throughput figure with no scenario cannot be placed against an MLPerf Offline or Server number (they are different measurements; on identical hardware the Offline-minus-Server difference is negative in 5 of 9 systems measured). ABSENT CONDITIONS (5 of 7 checked: model, hardware, batch-or-concurrency, input length, output length, engine version, warmup): - engine version: unrecoverable from asic-tpu-v6e-specs - engine_id=alt-tpu-perf-guide is named but no build/commit/container digest is published - batch/concurrency: unrecoverable from asic-tpu-v6e-specs - would need the achieved in-flight batch or the --max-concurrency value - input length: unrecoverable from asic-tpu-v6e-specs - would need the run's ISL or the prepared dataset's input-length profile - output length: unrecoverable from asic-tpu-v6e-specs - would need the run's OSL or the harness's configured max_tokens - warmup: unrecoverable from asic-tpu-v6e-specs - would need the raw harness log's warmup phase or the benchmark command line (loadgen min_duration/min_query_count, or trtllm-bench --warm_up N / --num_runs N) None of these were filled in. A plausible value is worse than an absent one: it would be trusted. METRIC KEY AUDIT 2026-10-05 (agent w6-benchmarks): VALUE UNCHANGED. metric=tps_aggregate carries a theoretical BF16 peak of 918 TFLOPS per chip, not a tokens/s rate. See data/gotchas/bench-tflops-filed-as-tps-aggregate-survives-the-tok-s-filter.json.